NCP1360, NCP1365
Low Power Offline Constant
Current & Constant Voltage
Primary Side PWM
Current-Mode Controller
with/without High Voltage
Startup Current Source
The NCP1360/65 offers a new solution targeting output power
levels from a few watts up to 20 W in a universal−mains flyback
application. Thanks to a novel method this new controller saves the
secondary feedback circuitry (opto−coupler and TL431 reference)
while achieving excellent line and load regulation.
The NCP1360/65 operates in valley−lockout quasi−resonant peak
current mode control mode at nominal load to provide high efficiency.
When the secondary−side power starts diminishing, the switching
frequency naturally increases until a voltage−controlled oscillator
(VCO) takes the lead, synchronizing the MOSFET turn−on in a
drain−source voltage valley. The frequency is thus reduced by
stepping into successive valleys until the number 4 is reached. Beyond
this point, the frequency is linearly decreased in valley−switching
mode until a minimum is hit. This technique keeps the output in
regulation with the tiniest dummy load. Valley lockout during the first
four drain−source valleys prevents erratic discrete jumps and provides
good efficiency in lighter load situations.
Features
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MARKING
DIAGRAMS
8
SOIC−7
CASE 751U
1
TSOP−6
CASE 318G
1
A
L
Y
W
G
1
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
XXXXX
ALYWX
G
xxxAYWG
G
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information on page 27 of
this data sheet.
•
Primary−Side Feedback Eliminates Opto−coupler and TL431
•
•
•
•
•
•
•
•
•
•
•
•
Reference
±5%
Voltage Regulation
±10%
Current Regulation
560 V Startup Current Source
No Frequency Clamp, 80 or 110 kHz Maximum
Switching Frequency Options
Quasi−Resonant Operation with Valley Switching
Operation
Fixed Peak Current & Deep Frequency Foldback @
Light Load Operation
External Constant Voltage Feedback Adjustment
Cycle by Cycle Peak Current Limit
Build−In Soft−Start
Over & Under Output Voltage Protection
Cable Drop Compensation (None, 150 mV, 300 mV or
450 mV option)
Wide Operation
V
CC
R
ange (up to 28 V)
•
•
•
•
•
Low Start−up Current (2.5
mA
typ.) with NCP1360
Clamped Gate−drive Output for MOSFET
CS
&
Vs/ZCD
pin Short and Open Protection
Internal Temperature Shutdown
Less than 10 mW No−Load Performance at High Line
with NCP1365 Version
•
Less than 30 mW No−Load Performance at High Line
with NCP1360 Version
•
These are Pb−Free Devices
Typical Applications
•
Low power ac−dc Adapters for Chargers.
•
Ac−dc USB chargers for Cell Phones, Tablets and
Cameras
©
Semiconductor Components Industries, LLC, 2016
June, 2018
−
Rev. 7
1
Publication Order Number:
NCP1360/D
NCP1360, NCP1365
NCP1360
V
CC
1
6
V
S
/ZCD
V
S
/ZCD
COMP
GND
2
5
COMP
CS
DRV
3
(Top View)
4
CS
DRV
3
4
(Top View)
6
5
V
CC
GND
1
2
NCP1365
8
HV
Figure 1. Pin Connections
Ac
Ac
2
0
Vout
0
1
2
3
4
NCP1365
Vs/ZCD
Comp
CS
DRV
VCC
GND
6
5
HV
8
3
5
4
1
0
Figure 2. NCP1365 Typical Application Circuit
2
0
Ac
Ac
Out
0
3
5
4
5
6
NCP1360
CS
DRV
3
2
1
4
1
Comp GND
ZCD
Vcc
0
Figure 3. NCP1360 Typical Application Circuit
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2
NCP1360, NCP1365
I
HV
NCP1365 Only
HV
POReset
Double_Hiccup_ends
V
cc
V
cc(clamp)
R
lim
Latch
VCC and Logic
Management of
double hiccup
UVLO
V
dd
V
CC(Reset)
V
CC(OVP)
DbleHiccup
POReset
EN_UVP
Blanking
QR multi−mode
Valley lockout &
Valley Switching &
VCO management
Reset
Soft Start
SS
Vs /
ZCD
V
ref_CC
Zero Crossing &
Signal Sampling
CC
Control
Sampled V
out
SS
FB_CC
FB_CV
Control Law
&
Primary Peak
Current Control
V
CC(OVP)
FB
V
cc
UVLO
Clamp
S
Q
SCP
CBC
V
ref_CV1
OVP_Cmp
4 clk
Counter
DRV
R
126% V
ref_CV2
OVP
Comp
Latch
OTA
UVP_Cmp
V
UVP
V
CC(Reset)
S
Q
R
POReset
GND
V
ref_CV2
Peak current
Freeze
S
Q
EN_UVP
R
DbleHiccup
V
DD
I
CS
UVP
1/K
comp
FB Reset
I
CS_EN
CS
LEB1
Max_Ipk reset
Count
V
ILIM
POReset
DbleHiccup
LEB2
Reset
Counter
4 clk
Counter
SCP
OCP
Timer
OCP
Reset Timer
Note:
OVP: Over Voltage Protection
UVP: Under Voltage Protection
OCP: Over Current Protection
SCP: Short Circuit Protection
CBC: CaBle Compensation
t
LEB1
> t
LEB2
R
Q
S
V
CS(Stop)
CS pin Open (V
CS
> 2 V)
& Short (V
CS
< 50 mV)
detection is activated at
each startup
CS pin Fault
I
CS_EN
Figure 4. Functional Block Diagram: A Version
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3
NCP1360, NCP1365
PIN FUNCTION DESCRIPTION
Pin out
NCP1365
1
2
3
4
5
6
7
8
Pin out
NCP1360
6
5
4
3
2
1
−
−
Name
V
s
/ZCD
Comp
CS
DRV
GND
V
CC
NC
HV
Function
Connected to the auxiliary winding; this pin senses the voltage output for the primary
regulation and detects the core reset event for the Quasi−Resonant mode of operation.
This is the error amplifier output. The network connected between this pin and the
ground adjusts the regulation loop bandwidth.
This pin monitors the primary peak current.
Controller switch driver.
Ground reference.
This pin is connected to an external auxiliary voltage and supplies the controller.
Not Connected for creepage distance between high and low Voltage pins
Connected the high−voltage rail, this pin injects a constant current into the V
CC
capaci-
tor for starting−up the power supply.
MAXIMUM RATINGS
Symbol
V
CC(MAX)
ΔV
CC
/Δt
V
DRV(MAX)
I
DRV(MAX)
V
MAX
I
MAX
V
HV
R
θJ−A
T
J(MAX)
Rating
Maximum Power Supply voltage, VCC pin, continuous voltage
Maximum slew rate on V
CC
pin during startup phase
Maximum driver pin voltage, DRV pin, continuous voltage
Maximum current for DRV pin
Maximum voltage on low power pins (except pins DRV and VCC)
Current range for low power pins (except pins DRV and VCC)
High Voltage pin voltage
Thermal Resistance Junction−to−Air
Maximum Junction Temperature
Operating Temperature Range
Storage Temperature Range
Human Body Model ESD Capability per JEDEC JESD22−A114F
Machine Model ESD Capability (All pins except DRV) per JEDEC JESD22−A115C
Charged−Device Model ESD Capability per JEDEC JESD22−C101E
Value
−0.3
to 28
+0.4
−0.3,
V
DRV
(Note 1)
−300,
+500
−0.3,
5.5
−2,
+5
−0.3
to 560
200
150
−40
to +125
−60
to +150
2
200
500
Unit
V
V/ms
V
mA
V
mA
V
°C/W
°C
°C
°C
kV
V
V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. V
DRV
is the DRV clamp voltage V
DRV(high)
when V
CC
is higher than V
DRV(high)
. V
DRV
is V
CC
otherwise
2. This device contains latch−up protection and exceeds 100 mA per JEDEC Standard JESD78.
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4
NCP1360, NCP1365
ELECTRICAL CHARACTERISTICS:
(V
CC
= 12 V, C
DRV
= 1 nF, For typical values T
J
= 25°C, for min/max values T
J
=
−40°C
to
+125°C, Max T
J
= 150°C, unless otherwise noted)
Characteristics
Conditions
Symbol
Min
Typ
Max
Unit
HIGH VOLTAGE STARTUP SECTION (NCP1365 only)
Startup current sourced by V
CC
pin
Leakage current at HV
V
HV
= 100 V
V
HV
= 400 V, options NCP1365AABCY
and NCP1365BABCY
All other NCP1365 options
I
HV
= 95% of I
HV
@V
HV
= 100 V, V
CC
=
V
CC(on)
−
0.2 V
I
HV
I
HV_LKG
70
−
−
V
HV(min)
−
100
0.1
0.1
22
150
1.0
1.3
25
V
mA
mA
Minimum Start−up HV voltage
SUPPLY SECTION AND V
CC
MANAGEMENT
V
CC
level at which driving
pulses are authorized
V
CC
level at which driving
pulses are stopped
Internal Latch / Logic Reset
Level
V
CC
clamp level
V
CC
clamp level (A & C
version)
Minimal current into V
CC
pin
that keeps the controller
Latched (NCP1365, A & C fault
mode version)
Minimal current into V
CC
pin
that keeps the controller
Latched (NCP1360, A & C fault
mode version)
Current−limit resistor in series
with the latch SCR
Over Voltage Protection
Start−up supply current,
controller disabled or latched
(Only valid with NCP1360 )
Internal IC consumption,
steady state
Internal IC consumption,
frequency foldback mode
Internal IC consumption when
STBY mode is activated
Over Voltage threshold
V
CC
< V
CC(on)
& V
CC
increasing from 0 V
Activated after Latch protection @ I
CC
=
100
mA
V
CC
increasing
V
CC
decreasing
V
CC(on)
V
CC(off)
V
CC(reset)
16
6.0
−
18
6.5
5.6
20
7.0
−
V
V
V
V
CC(Clamp)
−
4.2
−
V
I
CC(Clamp)
−
−
20
mA
I
CC(Clamp)
−
−
6
mA
R
lim
V
CC(OVP)
I
CC1
−
24
−
7
26
2.5
−
28
5.0
kW
V
mA
F
sw
= 65 kHz, C
DRV
= 1 nF
VCO mode, Fsw = 1 kHz, C
DRV
= 1 nF
VCO mode, Fsw = f
VCO(min)
,
V
Comp
= GND, C
DRV
= 1 nF
f
VCO(min)
= 200 Hz
f
VCO(min)
= 600 Hz
f
VCO(min)
= 1.2 kHz
V
Comp
= V
Comp(max)
, V
CS
increasing
Options NCP1365AABCY,
NCP1365BABCY, NCP1360AABCY,
NCP1360BABCY only
all other options
V
CS
> (V
ILIM
+ 100 mV) to DRV turn−off
I
CC2
I
CC3
I
CC4
−
−
1.7
0.8
2.5
1.2
mA
mA
mA
−
−
−
200
220
270
250
280
330
CURRENT COMPARATOR
Current Sense Voltage
Threshold
Cycle by Cycle Leading Edge
Blanking Duration
V
ILIM
t
LEB1
0.76
250
240
t
ILIM
−
0.80
300
300
50
0.84
360
360
100
ns
V
ns
Cycle by Cycle Current Sense
Propagation Delay
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
3. The timer can be reset if there are 4 DRV cycles without overload or short circuit conditions
4. Guaranteed by Design.
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5
stm32/stm8
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