BLF8G22LS-200V;
BLF8G22LS-200GV
Power LDMOS transistor
Rev. 2 — 10 December 2012
Product data sheet
1. Product profile
1.1 General description
200 W LDMOS power transistor with improved video bandwidth for base station
applications at frequencies from 2110 MHz to 2170 MHz.
Table 1.
Typical performance
Typical RF performance at T
case
= 25
C in a common source class-AB production test circuit, tested
on straight lead device.
Test signal
2-carrier W-CDMA
[1]
f
(MHz)
2110 to 2170
I
Dq
(mA)
2000
V
DS
(V)
28
P
L(AV)
(W)
55
G
p
(dB)
19.0
D
(%)
29
ACPR
5M
(dBc)
30
[1]
3GPP test model 1; 64 DPCH; PAR = 8.4 dB at 0.01 % probability on CCDF; 5 MHz carrier spacing.
1.2 Features and benefits
Excellent ruggedness
High efficiency
Low R
th
providing excellent thermal stability
Designed for broadband operation
Decoupling leads to enable improved video bandwidth (80 MHz typical)
Lower output capacitance for improved performance in Doherty applications
Designed for low memory effects providing excellent pre-distortability
Internally matched for ease of use
Integrated ESD protection
Compliant to Directive 2002/95/EC, regarding Restriction of Hazardous Substances
(RoHS)
1.3 Applications
RF power amplifiers for base stations and multi carrier applications in the 2110 MHz to
2170 MHz frequency range
NXP Semiconductors
BLF8G22LS-200(G)V
Power LDMOS transistor
2. Pinning information
Table 2.
Pin
1
2
3
4
5
6
7
Pinning
Description
drain
gate
source
video lead
video lead
n.c.
n.c.
[1]
Simplified outline
Graphic symbol
BLF8G22LS-200V (SOT1244B)
DDD
BLF8G22LS-200GV (SOT1244C)
1
2
3
4
5
6
7
[1]
drain
gate
source
video lead
video lead
n.c.
n.c.
Connected to flange.
[1]
DDD
3. Ordering information
Table 3.
Ordering information
Package
Name Description
BLF8G22LS-200V
-
earless flanged ceramic package; 6 leads
earless flanged ceramic package; 6 leads
BLF8G22LS-200GV -
Version
SOT1244B
SOT1244C
Type number
4. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
V
DS
V
GS
T
stg
T
j
Parameter
drain-source voltage
gate-source voltage
storage temperature
junction temperature
Conditions
Min
-
0.5
65
-
Max
65
+13
+150
225
Unit
V
V
C
C
BLF8G22LS-200V_8G22LS-200GV
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 2 — 10 December 2012
2 of 16
NXP Semiconductors
BLF8G22LS-200(G)V
Power LDMOS transistor
5. Thermal characteristics
Table 5.
Symbol
R
th(j-c)
Thermal characteristics
Parameter
thermal resistance from junction to case
Conditions
T
case
= 80
C;
P
L
= 45 W
Typ
0.26
Unit
K/W
6. Characteristics
Table 6.
DC characteristics
T
j
= 25
C; per section unless otherwise specified.
Symbol Parameter
V
(BR)DSS
drain-source breakdown voltage
V
GS(th)
I
DSS
I
DSX
I
GSS
g
fs
R
DS(on)
gate-source threshold voltage
drain leakage current
drain cut-off current
gate leakage current
forward transconductance
drain-source on-state resistance
Conditions
V
GS
= 0 V; I
D
= 3.3 mA
V
DS
= 10 V; I
D
= 330 mA
V
GS
= 0 V; V
DS
= 28 V
V
GS
= V
GS(th)
+ 3.75 V;
V
DS
= 10 V
V
GS
= 11 V; V
DS
= 0 V
V
DS
= 10 V; I
D
= 330 mA
V
GS
= V
GS(th)
+ 3.75 V;
I
D
= 11.55 A
Min
65
1.5
-
-
-
-
-
Typ
-
1.8
-
Max Unit
-
2.3
4.2
V
V
A
A
nA
S
62.4 -
-
420
2.85 -
0.05 -
Table 7.
RF characteristics
Test signal: 2-carrier W-CDMA; PAR = 8.4 dB at 0.01 % probability on the CCDF; 3GPP test
model 1; 1-64 DPCH; f
1
= 2112.5 MHz; f
2
= 2117.5 MHz; f
3
= 2162.5 MHz; f
4
= 2167.5 MHz;
RF performance at V
DS
= 28 V; I
Dq
= 2000 mA; T
case
= 25
C; unless otherwise specified; in a
class-AB production test circuit, tested on straight lead device.
Symbol
G
p
RL
in
D
ACPR
5M
Parameter
power gain
input return loss
drain efficiency
adjacent channel power ratio (5 MHz)
Conditions
P
L(AV)
= 55 W
P
L(AV)
= 55 W
P
L(AV)
= 55 W
P
L(AV)
= 55 W
Min
17.8
-
26
-
Typ
13
29
30
Max
7
-
26
Unit
dB
dB
%
dBc
19.0 -
7. Test information
7.1 Ruggedness in class-AB operation
The BLF8G22LS-200V and BLF8G22LS-200GV are capable of withstanding a load
mismatch corresponding to VSWR = 10 : 1 through all phases under the following
conditions: V
DS
= 28 V; I
Dq
= 2000 mA; P
L
= 200 W (CW); f = 2110 MHz.
BLF8G22LS-200V_8G22LS-200GV
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 2 — 10 December 2012
3 of 16
NXP Semiconductors
BLF8G22LS-200(G)V
Power LDMOS transistor
7.2 Impedance information
Table 8.
Typical impedance information
I
Dq
= 2000 mA; main transistor V
DS
= 28 V.
Z
S
and Z
L
defined in
Figure 1.
f
(MHz)
BLF8G22LS-200V
2110
2140
2170
BLF8G22LS-200GV
2110
2140
2170
0.77
j6.22
0.80
j6.34
1.00
j6.61
2.00
j4.20
2.33
j4.00
2.55
j4.00
0.84
j4.17
0.95
j4.43
1.12
j5.68
2.07
j2.39
2.23
j2.41
2.53
j2.40
Z
S
()
Z
L
()
drain
Z
L
gate
Z
S
001aaf059
Fig 1.
Definition of transistor impedance
BLF8G22LS-200V_8G22LS-200GV
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 2 — 10 December 2012
4 of 16
NXP Semiconductors
BLF8G22LS-200(G)V
Power LDMOS transistor
7.3 Test circuit
PP
PP
&
&
&
5
&
&
5
&
&
&
&
PP
&
&
5
&
&
&
&
&
DDD
Printed-Circuit Board (PCB): Rogers RO4350;
r
= 3.5; thickness = 0.76 mm, copper
plating = 35
m.
See
Table 9
for list of components.
Fig 2.
Component layout for test circuit
Table 9.
List of components
For test circuit, see
Figure 2.
Component
C1, C4, C7, C11, C14
C2
C3, C5, C16
C8, C13
C6, C9, C12, C15
C10
R1
R2, R3
Description
multilayer ceramic chip capacitor
multilayer ceramic chip capacitor
multilayer ceramic chip capacitor
multilayer ceramic chip capacitor
multilayer ceramic chip capacitor
electrolytic capacitor
resistor
resistor
Value
8.2 pF
1
F
100 nF
220 nF, 50 V
4.7
F,
50 V
>470
F,
50 V
2.2
0
Remarks
ATC100B;
vertically mounted
Murata
Murata
Murata
Murata
low ESR
SMD 0805;
tolerance = 1 %
SMD 0805
BLF8G22LS-200V_8G22LS-200GV
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 2 — 10 December 2012
5 of 16
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