BRP2-D-54-S-4-G2 datasheet, PDF

BRP2-D-54-S-4-G2: DescriptionHEADER CONNECTOR,PCB MNT,RECEPT,54 CONTACTS,PIN,0.1 PITCH,WRAP POST TERMINAL,BLACK; CategoryThe connector The connector; File Size153KB，2 Pages; ManufacturerCooper Industries

Download Datasheet Parametric View All

BRP2-D-54-S-4-G2 Overview

HEADER CONNECTOR,PCB MNT,RECEPT,54 CONTACTS,PIN,0.1 PITCH,WRAP POST TERMINAL,BLACK

Parameter Name	Attribute value
Maker	Cooper Industries
Reach Compliance Code	unknown
ECCN code	EAR99
body width	0.2 inch
subject depth	0.1 inch
body length	2.699 inch
Body/casing type	RECEPTACLE
Connector type	BOARD CONNECTOR
Contact to complete cooperation	AU ON NI
Contact completed and terminated	GOLD
Contact point gender	MALE
Contact material	PHOSPHOR BRONZE
contact mode	RECTANGULAR
Contact style	SQ PIN-SKT
Insulator color	BLACK
insulator material	GLASS FILLED THERMOPLASTIC
Manufacturer's serial number	BRP2
Plug contact pitch	0.1 inch
Match contact row spacing	0.1 inch
Installation method	STRAIGHT
Installation type	BOARD
Number of connectors	ONE
PCB row number	2
Number of rows loaded	2
PCB contact pattern	RECTANGULAR
PCB contact row spacing	2.54 mm
Guideline	UL
reliability	COMMERCIAL
Terminal length	0.425 inch
Terminal pitch	2.54 mm
Termination type	WIRE WRAP
Total number of contacts	54

How to understand keeping time negative: Why is the hold time negative? Is it because the clock frequency is too high? By the way, you can see the minimum hold time bit 0 on the DATASHEET provided by ALTAER. From the definition of hold time,...; eeleader FPGA/CPLD

Electronic combination lock: The course design requires making an electronic password lock, but the one I made cannot change the password and power-off protection. The teacher said it is not qualified! Experts, please help me sen...; yanyang1127 Embedded System

Verilog programming using D flip-flops to generate fixed sequences: As shown in the picture below, I use D flip-flops to form a shift register to generate a fixed sequence 10001110. There is no error in the rtl circuit diagram, but the simulation on modelsim only has ...; cmflyme FPGA/CPLD

Threshold setting for A/D high-speed acquisition of analog signals: Source: Single-chip microcomputer and embedded system applicationAuthor: Li Daguo and Zhang Qingming, Beijing Institute of Technology The A/D conversion interface circuit is a link in the forward chan...; fighting Analog electronics

From CC2530 to CC2530+CC2591: From CC2530 to CC2530+CC2591, in addition to changing #define xHAL_PA_LNA to #define HAL_PA_LNAWhat other settings are there?...; ljt8015 RF/Wirelessly

Apply for LMR24220 power module: I have recently become fascinated with electronic gadgets. I like to use breadboards and discrete components to build some experimental circuits. However, some experimental circuits require a relative...; lcofjp Power technology

Shortcut: S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 SA SB SC SD SE SF SG SH SI SJ SK SL SM SN SO SP SQ SR SS ST SU SV SW SX SY SZ T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 TA TB TC TD TE TF TG TH TI TJ TK TL TM TN TO TP TQ TR TS TT TU TV TW TX TY TZ U0 U1 U2 U3 U4 U6 U7 U8 UA UB UC UD UE UF UG UH UI UJ UK UL UM UN UP UQ UR US UT UU UV UW UX UZ V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 VA VB VC VD VE VF VG VH VI VJ VK VL VM VN VO VP VQ VR VS VT VU VV VW VX VY VZ W0 W1 W2 W3 W4 W5 W6 W7 W8 W9 WA WB WC WD WE WF WG WH WI WJ WK WL WM WN WO WP WR WS WT WU WV WW WY X0 X1 X2 X3 X4 X5 X7 X8 X9 XA XB XC XD XE XF XG XH XK XL XM XN XO XP XQ XR XS XT XU XV XW XX XY XZ Y0 Y1 Y2 Y4 Y5 Y6 Y9 YA YB YC YD YE YF YG YH YK YL YM YN YP YQ YR YS YT YX Z0 Z1 Z2 Z3 Z4 Z5 Z6 Z8 ZA ZB ZC ZD ZE ZF ZG ZH ZJ ZL ZM ZN ZP ZR ZS ZT ZU ZV ZW ZX ZY

Popular Components