LH7A404
Preliminary data sheet
FEATURES
• 32-bit ARM9TDMI™ RISC Core
– 16 kB Cache: 8 kB Instruction and 8 kB Data Cache
– MMU (Windows CE™ Enabled)
– Up to 266 MHz; See Table 1 for speed options
• 80 kB On-Chip Static RAM
• Vectored Interrupt Controller
• External Bus Interface
– Up to 133 MHz; See Table 1 for bus speed options
– Asynchronous and Synchronous interface RAM,
Flash, PC Card and CompactFlash
• Clock and Power Management
– 32.768 kHz and 14.7456 MHz Oscillators
– Programmable PLL
• Programmable LCD Controller
– Up to 1,024 × 768 Resolution
– Supports STN, Color STN, AD-TFT, HR-TFT, TFT
– Up to 64 K-Colors and 15 Gray Shades
• 9 Channel, 10-bit A/D Converter
– Touch Screen Controller
– Brownout Detector
• DMA (12 Channels)
– External DMA Channels
– AC97
– MMC
– USB
• USB 2.0 Full Speed Host (two downstream ports)
• USB 2.0 Full Speed Device
• Synchronous Serial Port (SSP)
– Motorola SPI™, Texas Instruments SSI, National
Semiconductor MICROWIRE™
• On-board Boot ROM
– Variety of Boot Modes: external ROM, NAND
Flash, Serial EEPROM, or XMODEM
• PS/2 Keyboard/Mouse Interface (KMI)
32-Bit System-on-Chip
• Three Programmable Timers
• Three UARTs, one with Classic IrDA (115 kbit/s)
• Smart Card Interface (ISO7816)
• Four Pulse Width Modulators (PWMs)
• MultiMediaCard Interface with Secure Digital
(MMC 2.11/SD 1.0)
• AC97 Codec Interface
• Smart Battery Monitor Interface
• Real Time Clock (RTC)
• Up to 64 General Purpose I/O Channels
• Watchdog Timer
• JTAG Debug Interface and Boundary Scan
• Operating Voltage
– 1.8 V (200 MHz), 2.1 V (266 MHz) Core
– 3.3 V Input/Output (Except XTALIN is 1.8 V)
• 5 V Tolerant Digital Inputs (excludes oscillator pins)
– Oscillator pins T19, T20, Y18, Y19: 1.8 V ± 10 %
• Operating Temperature:
−40°C
to +85°C
• 324-Ball LFBGA Package
DESCRIPTION
The advent of 3G technology opens up a wide range
of multimedia applications in mobile information appli-
ances. The LH7A404 is designed from the ground up
with a 32-bit ARM922 Core to provide high processing
performance, low power consumption, and a high level
of integration. Features include 80 kB on-chip SRAM,
fully static design, power management unit, low voltage
(1.8 V Core, 3.3 V I/O) and on-chip PLL.
NOTE:
Devices containing lead-free solder formulations have differ-
ent reflow temperatures than leaded-solder formulations.
When using both solder formulations on the same PC board,
designers should consider the effect of different reflow tem-
peratures on the overall PCB assembly process. (Refer to
www.nxp.com for an application note on recommended
soldering practices).
Table 1. LH7A404 Versions
PART NUMBER
1
LH7A404-N0F-092-xx
2
LH7A404-N0F-000-xx
2
CORE CLOCK BUS CLOCK
266 MHz
200 MHz
133 MHz
100 MHz
LOW POWER CURRENT BY MODE
Run = 228 mA (Typ.); Halt = 60 mA (Typ.);
Standby = 200
µA
(Typ.)
Run = 147 mA (Typ.); Halt = 41 mA (Typ.);
Standby = 70
µA
(Typ.)
VERSION
SOT1021-1
SOT1021-1
NOTES:
1. Where ‘xx’ is a two digit revision number, e.g. B2; refer to
www.NXP.com for a list of all the active revisions
2. Lead-free part.
Preliminary data sheet
1
LH7A404
NXP Semiconductors
32-Bit System-on-Chip
Table 2. LH7A404 Functional Pin List (Cont’d)
LFBGA
E6
E15
F5
F16
J16
M5
R5
R16
T6
T15
Y17
W17
V16
U15
W16
V13
D2
E1
F3
F4
C1
C5
Y18
Y19
T19
T20
L2
T16
Y13
VDDA
Analog Power for PLL1 and PLL2
VSSC
Core Ground
SIGNAL
DESCRIPTION
RESET
STATE
STANDBY
STATE
OUTPUT
DRIVE I/O NOTES
VSSA
VDDAD
VSSAD
nPOR
nURESET
WAKEUP
nPWRFL
nEXTPWR
nRESETOUT
XTALIN
XTALOUT
XTAL32IN
XTAL32OUT
PGMCLK
CLKEN
WIDTH0
Analog Ground for PLL1 and PLL2
Analog Power for A/D, Touch Screen Controller
Analog Ground for A/D, Touch Screen Controller
Power on Reset
User Reset
Wake Up
Power Fail Signal
External Power
Reset Output to external devices. This pin carries the
same state as the internal SoC reset signal.
14.7456 MHz Crystal Oscillator pins. For an external
clock source, XTALIN can be used while XTALOUT is
left unconnected. XTALIN voltage is 1.8 V nominal.
32.768 kHz Real Time Clock, Crystal Oscillator pins.
To drive the device from an external clock source,
XTAL32IN can be used while XTAL32OUT is left
unconnected.
Programmable Clock (14.7456 MHz MAX.)
External Oscillator Enable Output
Boot Width Pins. Used with the MEDCHG and INT-
BOOT bits for internal Boot ROM. On power up, the
values on these pins are latched to determine the
width and type of Boot device. Boot width can be 8-,
16-, or 32-bit. The pins must be pulled HIGH with a 33
kΩ resistor.
Media Change bit; used at power on with INTBOOT
and WIDTHx pins to determine boot device.
When LOW, boot device is selected according to the
MEDCHG bit. When HIGH, the lower 64 kB address-
es are mapped to the internal Boot ROM.
LOW
LOW
LOW
LOW
8 mA
8 mA
O
I/O
Input
Input
Input
Input
Input
LOW
Input
Input
Input
Input
Input
12 mA
I
I
I
I
I
O
3
3
3
3
3
Input
Input
I
3
W13
WIDTH1
E4
MEDCHG
Input
No Change
I
3
Y20
INTBOOT
Input
No Change
I
4
Preliminary data sheet
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