LM3S1110-IRN25-B0 datasheet, PDF

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LM3S1110-IRN25-B0: Description32-BIT, FLASH, RISC MICROCONTROLLER, PQFP100; Categorysemiconductor The embedded processor and controller; File Size3MB，377 Pages; ManufacturerETC2

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LM3S1110-IRN25-B0 Overview

32-BIT, FLASH, RISC MICROCONTROLLER, PQFP100

LM3S1110-IRN25-B0 Parametric

Parameter Name	Attribute value
Number of terminals	100
Maximum operating temperature	85 Cel
Maximum supply/operating voltage	2.75 V
Minimum supply/operating voltage	2.25 V
Rated supply voltage	2.5 V
External data bus width	0.0
Number of input and output buses	41
Line speed	25 MHz
Processing package description	Green, MS-026BED, LQFP-100
Lead-free	Yes
EU RoHS regulations	Yes
China RoHS regulations	Yes
state	ACTIVE
packaging shape	SQUARE
Package Size	FLATPACK
surface mount	Yes
Terminal form	GULL WING
Terminal spacing	0.5000 mm
terminal coating	tin
Terminal location	Four
Packaging Materials	Plastic/Epoxy
Temperature level	INDUSTRIAL
ADC channel	Yes
Address bus width	0.0
Number of digits	32
Maximum FCLK clock frequency	0.0320 MHz
Microprocessor type	Reduced Instruction Set Microcontroller
PWM channel	Yes
ROM programming	FLASH

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LM3S1110 Microcontroller

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LM3S1110 Microcontroller

Table of Contents

About This Document .................................................................................................................... 15

Audience ..............................................................................................................................................

About This Manual ................................................................................................................................

Related Documents ...............................................................................................................................

Documentation Conventions ..................................................................................................................

1.1

1.2

1.3

1.4

1.4.1

1.4.2

1.4.3

1.4.4

1.4.5

1.4.6

1.4.7

1.4.8

Architectural Overview ...................................................................................................... 17

Product Features ......................................................................................................................

Target Applications ....................................................................................................................

High-Level Block Diagram .........................................................................................................

Functional Overview ..................................................................................................................

ARM Cortex™-M3 .....................................................................................................................

Motor Control Peripherals ..........................................................................................................

Analog Peripherals ....................................................................................................................

Serial Communications Peripherals ............................................................................................

System Peripherals ...................................................................................................................

Memory Peripherals ..................................................................................................................

Additional Features ...................................................................................................................

Hardware Details ......................................................................................................................

Block Diagram ..........................................................................................................................

Functional Description ...............................................................................................................

Serial Wire and JTAG Debug .....................................................................................................

Embedded Trace Macrocell (ETM) .............................................................................................

Trace Port Interface Unit (TPIU) .................................................................................................

ROM Table ...............................................................................................................................

Memory Protection Unit (MPU) ...................................................................................................

Nested Vectored Interrupt Controller (NVIC) ................................................................................

2.1

2.2

2.2.1

2.2.2

2.2.3

2.2.4

2.2.5

2.2.6

ARM Cortex-M3 Processor Core ...................................................................................... 28

5.1

5.2

5.2.1

5.2.2

5.2.3

5.2.4

5.3

5.4

5.4.1

5.4.2

Memory Map ....................................................................................................................... 34

Interrupts ............................................................................................................................ 36

JTAG Interface .................................................................................................................... 38

Block Diagram ..........................................................................................................................

Functional Description ...............................................................................................................

JTAG Interface Pins ..................................................................................................................

JTAG TAP Controller .................................................................................................................

Shift Registers ..........................................................................................................................

Operational Considerations ........................................................................................................

Initialization and Configuration ...................................................................................................

Register Descriptions ................................................................................................................

Instruction Register (IR) .............................................................................................................

Data Registers ..........................................................................................................................

6.1

6.1.1

6.1.2

System Control ................................................................................................................... 49

Functional Description ............................................................................................................... 49

Device Identification .................................................................................................................. 49

Reset Control ............................................................................................................................ 49

September 02, 2007

Preliminary

Table of Contents

6.1.3

6.1.4

6.1.5

6.2

6.3

6.4

Power Control ...........................................................................................................................

Clock Control ............................................................................................................................

System Control .........................................................................................................................

Initialization and Configuration ...................................................................................................

Register Map ............................................................................................................................

Register Descriptions ................................................................................................................

Block Diagram ........................................................................................................................

Functional Description .............................................................................................................

Register Access Timing ...........................................................................................................

Clock Source ..........................................................................................................................

Battery Management ...............................................................................................................

Real-Time Clock ......................................................................................................................

Non-Volatile Memory ...............................................................................................................

Power Control .........................................................................................................................

Interrupts and Status ...............................................................................................................

Initialization and Configuration .................................................................................................

Initialization .............................................................................................................................

RTC Match Functionality (No Hibernation) ................................................................................

RTC Match/Wake-Up from Hibernation .....................................................................................

External Wake-Up from Hibernation ..........................................................................................

RTC/External Wake-Up from Hibernation ..................................................................................

Register Map ..........................................................................................................................

Register Descriptions ..............................................................................................................

7.1

7.2

7.2.1

7.2.2

7.2.3

7.2.4

7.2.5

7.2.6

7.2.7

7.3

7.3.1

7.3.2

7.3.3

7.3.4

7.3.5

7.4

7.5

Hibernation Module .......................................................................................................... 102

103

104

105

106

107

108

8.1

8.2

8.2.1

8.2.2

8.3

8.3.1

8.3.2

8.4

8.5

8.6

Internal Memory ............................................................................................................... 121

Block Diagram ........................................................................................................................ 121

Functional Description ............................................................................................................. 121

SRAM Memory ........................................................................................................................ 121

Flash Memory ......................................................................................................................... 122

Flash Memory Initialization and Configuration ........................................................................... 123

Flash Programming ................................................................................................................. 123

Nonvolatile Register Programming ........................................................................................... 124

Register Map .......................................................................................................................... 124

Flash Register Descriptions (Flash Control Offset) ..................................................................... 125

Flash Register Descriptions (System Control Offset) .................................................................. 132

9.1

9.1.1

9.1.2

9.1.3

9.1.4

9.1.5

9.1.6

9.2

9.3

9.4

General-Purpose Input/Outputs (GPIOs) ....................................................................... 145

Functional Description ............................................................................................................. 145

Data Control ........................................................................................................................... 145

Interrupt Control ...................................................................................................................... 146

Mode Control .......................................................................................................................... 147

Commit Control ....................................................................................................................... 147

Pad Control ............................................................................................................................. 147

Identification ........................................................................................................................... 147

Initialization and Configuration ................................................................................................. 147

Register Map .......................................................................................................................... 148

Register Descriptions .............................................................................................................. 150

Preliminary

September 02, 2007

LM3S1110 Microcontroller

10.1

10.2

10.2.1

10.2.2

10.2.3

10.3

10.3.1

10.3.2

10.3.3

10.3.4

10.3.5

10.3.6

10.4

10.5

General-Purpose Timers ................................................................................................. 185

Block Diagram ........................................................................................................................

Functional Description .............................................................................................................

GPTM Reset Conditions ..........................................................................................................

32-Bit Timer Operating Modes ..................................................................................................

16-Bit Timer Operating Modes ..................................................................................................

Initialization and Configuration .................................................................................................

32-Bit One-Shot/Periodic Timer Mode .......................................................................................

32-Bit Real-Time Clock (RTC) Mode .........................................................................................

16-Bit One-Shot/Periodic Timer Mode .......................................................................................

16-Bit Input Edge Count Mode .................................................................................................

16-Bit Input Edge Timing Mode ................................................................................................

16-Bit PWM Mode ...................................................................................................................