PR E LI MIN ARY
LM3S2739 Microcontroller
DATA SHEE T
DS-LM3S2 739-0 1
Cop yr igh t
©
2 00 7 L umin ary Mi cro , In c.
Legal Disclaimers and Trademark Information
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH LUMINARY MICRO PRODUCTS. NO LICENSE, EXPRESS
OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT.
EXCEPT AS PROVIDED IN LUMINARY MICRO'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, LUMINARY MICRO
ASSUMES NO LIABILITY WHATSOEVER, AND LUMINARY MICRO DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING
TO SALE AND/OR USE OF LUMINARY MICRO'S PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR
A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL
PROPERTY RIGHT. LUMINARY MICRO'S PRODUCTS ARE NOT INTENDED FOR USE IN MEDICAL, LIFE SAVING, OR LIFE-SUSTAINING
APPLICATIONS.
Luminary Micro may make changes to specifications and product descriptions at any time, without notice. Contact your local Luminary Micro
sales office or your distributor to obtain the latest specifications before placing your product order.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Luminary Micro
reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes
to them.
Copyright © 2007 Luminary Micro, Inc. All rights reserved. Stellaris is a registered trademark and Luminary Micro and the Luminary Micro
logo are trademarks of Luminary Micro, Inc. or its subsidiaries in the United States and other countries. ARM and Thumb are registered
trademarks and Cortex is a trademark of ARM Limited. Other names and brands may be claimed as the property of others.
Luminary Micro, Inc.
108 Wild Basin, Suite 350
Austin, TX 78746
Main: +1-512-279-8800
Fax: +1-512-279-8879
http://www.luminarymicro.com
2
Preliminary
June 04, 2007
LM3S2739 Microcontroller
Table of Contents
About This Document .................................................................................................................... 21
Audience ..............................................................................................................................................
About This Manual ................................................................................................................................
Related Documents ...............................................................................................................................
Documentation Conventions ..................................................................................................................
21
21
21
21
23
29
29
30
31
31
32
34
34
35
36
38
38
38
39
39
39
39
39
1
1.1
1.2
1.3
1.4
1.4.1
1.4.2
1.4.3
1.4.4
1.4.5
1.4.6
1.4.7
Overview ............................................................................................................................. 23
Product Features ......................................................................................................................
Target Applications ....................................................................................................................
High-Level Block Diagram .........................................................................................................
Functional Overview ..................................................................................................................
ARM Cortex™-M3 .....................................................................................................................
Motor Control Peripherals ..........................................................................................................
Serial Communications Peripherals ............................................................................................
System Peripherals ...................................................................................................................
Memory Peripherals ..................................................................................................................
Additional Features ...................................................................................................................
Hardware Details ......................................................................................................................
Block Diagram ..........................................................................................................................
Functional Description ...............................................................................................................
Serial Wire and JTAG Debug .....................................................................................................
Embedded Trace Macrocell (ETM) .............................................................................................
Trace Port Interface Unit (TPIU) .................................................................................................
ROM Table ...............................................................................................................................
Memory Protection Unit (MPU) ...................................................................................................
Nested Vectored Interrupt Controller (NVIC) ................................................................................
2
2.1
2.2
2.2.1
2.2.2
2.2.3
2.2.4
2.2.5
2.2.6
Cortex-M3 Core .................................................................................................................. 37
3
4
5
5.1
5.2
5.2.1
5.2.2
5.2.3
5.2.4
5.3
5.4
5.4.1
5.4.2
Memory Map ....................................................................................................................... 43
Interrupts ............................................................................................................................ 45
JTAG .................................................................................................................................... 48
Block Diagram ..........................................................................................................................
Functional Description ...............................................................................................................
JTAG Interface Pins ..................................................................................................................
JTAG TAP Controller .................................................................................................................
Shift Registers ..........................................................................................................................
Operational Considerations ........................................................................................................
Initialization and Configuration ...................................................................................................
Register Descriptions ................................................................................................................
Instruction Register (IR) .............................................................................................................
Data Registers ..........................................................................................................................
Functional Description ...............................................................................................................
Device Identification ..................................................................................................................
Reset Control ............................................................................................................................
Power Control ...........................................................................................................................
49
49
50
51
52
52
55
55
55
57
59
59
59
62
6
6.1
6.1.1
6.1.2
6.1.3
System Control ................................................................................................................... 59
June 04, 2007
Preliminary
3
Table of Contents
6.1.4
6.1.5
6.2
6.3
6.4
Clock Control ............................................................................................................................
System Control .........................................................................................................................
Initialization and Configuration ...................................................................................................
Register Map ............................................................................................................................
Register Descriptions ................................................................................................................
Block Diagram ........................................................................................................................
Functional Description .............................................................................................................
Register Access Timing ...........................................................................................................
Clock Source ..........................................................................................................................
Battery Management ...............................................................................................................
Real-Time Clock ......................................................................................................................
Non-Volatile Memory ...............................................................................................................
Power Control .........................................................................................................................
Interrupts and Status ...............................................................................................................
Initialization and Configuration .................................................................................................
Initialization .............................................................................................................................
RTC Match Functionality (No Hibernation) ................................................................................
RTC Match/Wake-Up from Hibernation .....................................................................................
External Wake-Up from Hibernation ..........................................................................................
RTC/External Wake-Up from Hibernation ..................................................................................
Register Map ..........................................................................................................................
Register Descriptions ..............................................................................................................
62
64
65
65
66
7
7.1
7.2
7.2.1
7.2.2
7.2.3
7.2.4
7.2.5
7.2.6
7.2.7
7.3
7.3.1
7.3.2
7.3.3
7.3.4
7.3.5
7.4
7.5
Hibernation Module .......................................................................................................... 113
114
114
114
115
115
115
116
116
116
116
117
117
117
117
118
118
118
8
8.1
8.2
8.2.1
8.2.2
8.3
8.3.1
8.3.2
8.4
8.5
Internal Memory ............................................................................................................... 131
Block Diagram ........................................................................................................................ 131
Functional Description ............................................................................................................. 131
SRAM Memory ........................................................................................................................ 131
Flash Memory ......................................................................................................................... 132
Flash Memory Initialization and Configuration ........................................................................... 133
Flash Programming ................................................................................................................. 133
Nonvolatile Register Programming ........................................................................................... 134
Register Map .......................................................................................................................... 134
Flash Register Descriptions ..................................................................................................... 135
9
9.1
9.1.1
9.1.2
9.1.3
9.1.4
9.1.5
9.1.6
9.2
9.3
9.4
GPIO .................................................................................................................................. 155
Function Description ................................................................................................................ 155
Data Control ........................................................................................................................... 155
Interrupt Control ...................................................................................................................... 156
Mode Control .......................................................................................................................... 157
Commit Control ....................................................................................................................... 157
Pad Control ............................................................................................................................. 157
Identification ........................................................................................................................... 158
Initialization and Configuration ................................................................................................. 158
Register Map .......................................................................................................................... 159
Register Descriptions .............................................................................................................. 161
10
10.1
10.2
Timers ............................................................................................................................... 196
Block Diagram ........................................................................................................................ 197
Functional Description ............................................................................................................. 197
4
Preliminary
June 04, 2007
LM3S2739 Microcontroller
10.2.1
10.2.2
10.2.3
10.3
10.3.1
10.3.2
10.3.3
10.3.4
10.3.5
10.3.6
10.4
10.5
GPTM Reset Conditions ..........................................................................................................
32-Bit Timer Operating Modes ..................................................................................................
16-Bit Timer Operating Modes ..................................................................................................
Initialization and Configuration .................................................................................................
32-Bit One-Shot/Periodic Timer Mode .......................................................................................
32-Bit Real-Time Clock (RTC) Mode .........................................................................................
16-Bit One-Shot/Periodic Timer Mode .......................................................................................
16-Bit Input Edge Count Mode .................................................................................................
16-Bit Input Edge Timing Mode ................................................................................................
16-Bit PWM Mode ...................................................................................................................
Register Map ..........................................................................................................................
Register Descriptions ..............................................................................................................
Block Diagram ........................................................................................................................
Functional Description .............................................................................................................
Initialization and Configuration .................................................................................................
Register Map ..........................................................................................................................
Register Descriptions ..............................................................................................................
197
197
199
203
203
204
204
205
205
206
206
207
229
229
230
230
231
11
11.1
11.2
11.3
11.4
11.5
Watchdog Timer ............................................................................................................... 229
12
12.1
12.2
12.2.1
12.2.2
12.2.3
12.2.4
12.2.5
12.2.6
12.3
12.3.1
12.3.2
12.4
12.5
ADC ................................................................................................................................... 252
Block Diagram ........................................................................................................................ 253
Functional Description ............................................................................................................. 253
Sample Sequencers ................................................................................................................ 253
Module Control ........................................................................................................................ 254
Hardware Sample Averaging Circuit ......................................................................................... 255
Analog-to-Digital Converter ...................................................................................................... 255
Test Modes ............................................................................................................................. 255
Internal Temperature Sensor .................................................................................................... 255
Initialization and Configuration ................................................................................................. 256
Module Initialization ................................................................................................................. 256
Sample Sequencer Configuration ............................................................................................. 256
Register Map .......................................................................................................................... 257
Register Descriptions .............................................................................................................. 258
13
13.1
13.2
13.2.1
13.2.2
13.2.3
13.2.4
13.2.5
13.2.6
13.2.7
13.2.8
13.3
13.4
13.5
UART ................................................................................................................................. 285
Block Diagram ........................................................................................................................
Functional Description .............................................................................................................
Transmit/Receive Logic ...........................................................................................................
Baud-Rate Generation .............................................................................................................
Data Transmission ..................................................................................................................
Serial IR (SIR) .........................................................................................................................
FIFO Operation .......................................................................................................................
Interrupts ................................................................................................................................
Loopback Operation ................................................................................................................
IrDA SIR block ........................................................................................................................
Initialization and Configuration .................................................................................................
Register Map ..........................................................................................................................
Register Descriptions ..............................................................................................................
286
286
286
287
288
288
289
289
290
290
290
291
292
14
SSI ..................................................................................................................................... 325
June 04, 2007
Preliminary
5
RF/Wirelessly
京公网安备 11010802033920号
EEWORLD
