PR E LI MIN ARY
LM3S2965 Microcontroller
DATA SHEE T
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Preliminary
November 30, 2007
LM3S2965 Microcontroller
Table of Contents
About This Document .................................................................................................................... 21
Audience ..............................................................................................................................................
About This Manual ................................................................................................................................
Related Documents ...............................................................................................................................
Documentation Conventions ..................................................................................................................
21
21
21
21
23
29
30
31
31
31
32
33
34
35
36
36
39
39
39
40
40
40
40
40
1
1.1
1.2
1.3
1.4
1.4.1
1.4.2
1.4.3
1.4.4
1.4.5
1.4.6
1.4.7
1.4.8
Architectural Overview ...................................................................................................... 23
Product Features ......................................................................................................................
Target Applications ....................................................................................................................
High-Level Block Diagram .........................................................................................................
Functional Overview ..................................................................................................................
ARM Cortex™-M3 .....................................................................................................................
Motor Control Peripherals ..........................................................................................................
Analog Peripherals ....................................................................................................................
Serial Communications Peripherals ............................................................................................
System Peripherals ...................................................................................................................
Memory Peripherals ..................................................................................................................
Additional Features ...................................................................................................................
Hardware Details ......................................................................................................................
Block Diagram ..........................................................................................................................
Functional Description ...............................................................................................................
Serial Wire and JTAG Debug .....................................................................................................
Embedded Trace Macrocell (ETM) .............................................................................................
Trace Port Interface Unit (TPIU) .................................................................................................
ROM Table ...............................................................................................................................
Memory Protection Unit (MPU) ...................................................................................................
Nested Vectored Interrupt Controller (NVIC) ................................................................................
2
2.1
2.2
2.2.1
2.2.2
2.2.3
2.2.4
2.2.5
2.2.6
ARM Cortex-M3 Processor Core ...................................................................................... 38
3
4
5
5.1
5.2
5.2.1
5.2.2
5.2.3
5.2.4
5.3
5.4
5.4.1
5.4.2
Memory Map ....................................................................................................................... 44
Interrupts ............................................................................................................................ 46
JTAG Interface .................................................................................................................... 49
Block Diagram ..........................................................................................................................
Functional Description ...............................................................................................................
JTAG Interface Pins ..................................................................................................................
JTAG TAP Controller .................................................................................................................
Shift Registers ..........................................................................................................................
Operational Considerations ........................................................................................................
Initialization and Configuration ...................................................................................................
Register Descriptions ................................................................................................................
Instruction Register (IR) .............................................................................................................
Data Registers ..........................................................................................................................
50
50
51
52
53
53
56
56
56
58
6
6.1
6.1.1
6.1.2
System Control ................................................................................................................... 60
Functional Description ............................................................................................................... 60
Device Identification .................................................................................................................. 60
Reset Control ............................................................................................................................ 60
November 30, 2007
Preliminary
3
Table of Contents
6.1.3
6.1.4
6.1.5
6.2
6.3
6.4
Power Control ...........................................................................................................................
Clock Control ............................................................................................................................
System Control .........................................................................................................................
Initialization and Configuration ...................................................................................................
Register Map ............................................................................................................................
Register Descriptions ................................................................................................................
Block Diagram ........................................................................................................................
Functional Description .............................................................................................................
Register Access Timing ...........................................................................................................
Clock Source ..........................................................................................................................
Battery Management ...............................................................................................................
Real-Time Clock ......................................................................................................................
Non-Volatile Memory ...............................................................................................................
Power Control .........................................................................................................................
Interrupts and Status ...............................................................................................................
Initialization and Configuration .................................................................................................
Initialization .............................................................................................................................
RTC Match Functionality (No Hibernation) ................................................................................
RTC Match/Wake-Up from Hibernation .....................................................................................
External Wake-Up from Hibernation ..........................................................................................
RTC/External Wake-Up from Hibernation ..................................................................................
Register Map ..........................................................................................................................
Register Descriptions ..............................................................................................................
63
63
65
66
66
67
7
7.1
7.2
7.2.1
7.2.2
7.2.3
7.2.4
7.2.5
7.2.6
7.2.7
7.3
7.3.1
7.3.2
7.3.3
7.3.4
7.3.5
7.4
7.5
Hibernation Module .......................................................................................................... 121
122
122
122
123
123
123
124
124
124
125
125
125
125
126
126
126
127
8
8.1
8.2
8.2.1
8.2.2
8.3
8.3.1
8.3.2
8.4
8.5
8.6
Internal Memory ............................................................................................................... 140
Block Diagram ........................................................................................................................ 140
Functional Description ............................................................................................................. 140
SRAM Memory ........................................................................................................................ 140
Flash Memory ......................................................................................................................... 141
Flash Memory Initialization and Configuration ........................................................................... 142
Flash Programming ................................................................................................................. 142
Nonvolatile Register Programming ........................................................................................... 143
Register Map .......................................................................................................................... 143
Flash Register Descriptions (Flash Control Offset) ..................................................................... 144
Flash Register Descriptions (System Control Offset) .................................................................. 151
9
9.1
9.1.1
9.1.2
9.1.3
9.1.4
9.1.5
9.1.6
9.2
9.3
9.4
General-Purpose Input/Outputs (GPIOs) ....................................................................... 164
Functional Description ............................................................................................................. 164
Data Control ........................................................................................................................... 165
Interrupt Control ...................................................................................................................... 166
Mode Control .......................................................................................................................... 167
Commit Control ....................................................................................................................... 167
Pad Control ............................................................................................................................. 167
Identification ........................................................................................................................... 167
Initialization and Configuration ................................................................................................. 167
Register Map .......................................................................................................................... 169
Register Descriptions .............................................................................................................. 170
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Preliminary
November 30, 2007
LM3S2965 Microcontroller
10
10.1
10.2
10.2.1
10.2.2
10.2.3
10.3
10.3.1
10.3.2
10.3.3
10.3.4
10.3.5
10.3.6
10.4
10.5
General-Purpose Timers ................................................................................................. 205
Block Diagram ........................................................................................................................
Functional Description .............................................................................................................
GPTM Reset Conditions ..........................................................................................................
32-Bit Timer Operating Modes ..................................................................................................
16-Bit Timer Operating Modes ..................................................................................................
Initialization and Configuration .................................................................................................
32-Bit One-Shot/Periodic Timer Mode .......................................................................................
32-Bit Real-Time Clock (RTC) Mode .........................................................................................
16-Bit One-Shot/Periodic Timer Mode .......................................................................................
16-Bit Input Edge Count Mode .................................................................................................
16-Bit Input Edge Timing Mode ................................................................................................
16-Bit PWM Mode ...................................................................................................................
Register Map ..........................................................................................................................
Register Descriptions ..............................................................................................................
Block Diagram ........................................................................................................................
Functional Description .............................................................................................................
Initialization and Configuration .................................................................................................
Register Map ..........................................................................................................................
Register Descriptions ..............................................................................................................
205
206
207
207
208
212
212
213
213
214
214
215
215
216
241
241
242
242
243
11
11.1
11.2
11.3
11.4
11.5
Watchdog Timer ............................................................................................................... 241
12
12.1
12.2
12.2.1
12.2.2
12.2.3
12.2.4
12.2.5
12.2.6
12.3
12.3.1
12.3.2
12.4
12.5
Analog-to-Digital Converter (ADC) ................................................................................. 264
Block Diagram ........................................................................................................................ 265
Functional Description ............................................................................................................. 265
Sample Sequencers ................................................................................................................ 265
Module Control ........................................................................................................................ 266
Hardware Sample Averaging Circuit ......................................................................................... 267
Analog-to-Digital Converter ...................................................................................................... 267
Test Modes ............................................................................................................................. 267
Internal Temperature Sensor .................................................................................................... 267
Initialization and Configuration ................................................................................................. 268
Module Initialization ................................................................................................................. 268
Sample Sequencer Configuration ............................................................................................. 268
Register Map .......................................................................................................................... 269
Register Descriptions .............................................................................................................. 270
13
13.1
13.2
13.2.1
13.2.2
13.2.3
13.2.4
13.2.5
13.2.6
13.2.7
13.2.8
13.3
13.4
Universal Asynchronous Receivers/Transmitters (UARTs) ......................................... 297
Block Diagram ........................................................................................................................
Functional Description .............................................................................................................
Transmit/Receive Logic ...........................................................................................................
Baud-Rate Generation .............................................................................................................
Data Transmission ..................................................................................................................
Serial IR (SIR) .........................................................................................................................
FIFO Operation .......................................................................................................................
Interrupts ................................................................................................................................
Loopback Operation ................................................................................................................
IrDA SIR block ........................................................................................................................
Initialization and Configuration .................................................................................................
Register Map ..........................................................................................................................
298
298
298
299
300
300
301
301
302
302
302
303
November 30, 2007
Preliminary
5
Analogue and Mixed Signal
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