LM3S300-IRN20-A1 datasheet, PDF

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LM3S300-IRN20-A1: DescriptionMicrocontroller; File Size3MB，378 Pages; ManufacturerETC2

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LM3S300-IRN20-A1 Overview

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PR E LI MIN ARY

LM3S300 Microcontroller

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LM3S300 Microcontroller

Table of Contents

About This Document .................................................................................................................... 15

Audience ..............................................................................................................................................

About This Manual ................................................................................................................................

Related Documents ...............................................................................................................................

Documentation Conventions ..................................................................................................................

1.1

1.2

1.3

1.4

1.4.1

1.4.2

1.4.3

1.4.4

1.4.5

1.4.6

1.4.7

1.4.8

Architectural Overview ...................................................................................................... 17

Product Features ......................................................................................................................

Target Applications ....................................................................................................................

High-Level Block Diagram .........................................................................................................

Functional Overview ..................................................................................................................

ARM Cortex™-M3 .....................................................................................................................

Motor Control Peripherals ..........................................................................................................

Analog Peripherals ....................................................................................................................

Serial Communications Peripherals ............................................................................................

System Peripherals ...................................................................................................................

Memory Peripherals ..................................................................................................................

Additional Features ...................................................................................................................

Hardware Details ......................................................................................................................

Block Diagram ..........................................................................................................................

Functional Description ...............................................................................................................

Serial Wire and JTAG Debug .....................................................................................................

Embedded Trace Macrocell (ETM) .............................................................................................

Trace Port Interface Unit (TPIU) .................................................................................................

ROM Table ...............................................................................................................................

Memory Protection Unit (MPU) ...................................................................................................

Nested Vectored Interrupt Controller (NVIC) ................................................................................

2.1

2.2

2.2.1

2.2.2

2.2.3

2.2.4

2.2.5

2.2.6

ARM Cortex-M3 Processor Core ...................................................................................... 28

5.1

5.2

5.2.1

5.2.2

5.2.3

5.2.4

5.3

5.4

5.4.1

5.4.2

Memory Map ....................................................................................................................... 34

Interrupts ............................................................................................................................ 36

JTAG Interface .................................................................................................................... 38

Block Diagram ..........................................................................................................................

Functional Description ...............................................................................................................

JTAG Interface Pins ..................................................................................................................

JTAG TAP Controller .................................................................................................................

Shift Registers ..........................................................................................................................

Operational Considerations ........................................................................................................

Initialization and Configuration ...................................................................................................

Register Descriptions ................................................................................................................

Instruction Register (IR) .............................................................................................................

Data Registers ..........................................................................................................................

6.1

6.1.1

6.1.2

System Control ................................................................................................................... 48

Functional Description ............................................................................................................... 48

Device Identification .................................................................................................................. 48

Reset Control ............................................................................................................................ 48

October 01, 2007

Preliminary

Table of Contents

6.1.3

6.1.4

6.1.5

6.2

6.3

6.4

Power Control ...........................................................................................................................

Clock Control ............................................................................................................................

System Control .........................................................................................................................

Initialization and Configuration ...................................................................................................

Register Map ............................................................................................................................

Register Descriptions ................................................................................................................

7.1

7.2

7.2.1

7.2.2

7.3

7.3.1

7.3.2

7.4

7.5

7.6

Internal Memory ............................................................................................................... 103

Block Diagram ........................................................................................................................ 103

Functional Description ............................................................................................................. 103

SRAM Memory ........................................................................................................................ 103

Flash Memory ......................................................................................................................... 104

Flash Memory Initialization and Configuration ........................................................................... 106

Changing Flash Protection Bits ................................................................................................ 106

Flash Programming ................................................................................................................. 107

Register Map .......................................................................................................................... 107

Flash Register Descriptions (Flash Control Offset) ..................................................................... 108

Flash Register Descriptions (System Control Offset) .................................................................. 115

8.1

8.1.1

8.1.2

8.1.3

8.1.4

8.1.5

8.2

8.3

8.4

General-Purpose Input/Outputs (GPIOs) ....................................................................... 119

Functional Description ............................................................................................................. 119

Data Control ........................................................................................................................... 120

Interrupt Control ...................................................................................................................... 121

Mode Control .......................................................................................................................... 122

Pad Control ............................................................................................................................. 122

Identification ........................................................................................................................... 122

Initialization and Configuration ................................................................................................. 122

Register Map .......................................................................................................................... 123

Register Descriptions .............................................................................................................. 125

9.1

9.2

9.2.1

9.2.2

9.2.3

9.3

9.3.1

9.3.2

9.3.3

9.3.4

9.3.5

9.3.6

9.4

9.5

General-Purpose Timers ................................................................................................. 157

Block Diagram ........................................................................................................................

Functional Description .............................................................................................................

GPTM Reset Conditions ..........................................................................................................

32-Bit Timer Operating Modes ..................................................................................................

16-Bit Timer Operating Modes ..................................................................................................

Initialization and Configuration .................................................................................................

32-Bit One-Shot/Periodic Timer Mode .......................................................................................

32-Bit Real-Time Clock (RTC) Mode .........................................................................................

16-Bit One-Shot/Periodic Timer Mode .......................................................................................

16-Bit Input Edge Count Mode .................................................................................................

16-Bit Input Edge Timing Mode ................................................................................................

16-Bit PWM Mode ...................................................................................................................

Register Map ..........................................................................................................................

Register Descriptions ..............................................................................................................

Block Diagram ........................................................................................................................

Functional Description .............................................................................................................

Initialization and Configuration .................................................................................................

Register Map ..........................................................................................................................

158

160

164

165

166

167

168

193

194

10.1

10.2

10.3

10.4

Watchdog Timer ............................................................................................................... 193

Preliminary

October 01, 2007

LM3S300 Microcontroller

10.5

Register Descriptions .............................................................................................................. 195

11.1

11.2

11.2.1

11.2.2

11.2.3

11.2.4

11.2.5

11.2.6

11.3

11.4

11.5

Universal Asynchronous Receivers/Transmitters (UARTs) ......................................... 216

Block Diagram ........................................................................................................................

Functional Description .............................................................................................................

Transmit/Receive Logic ...........................................................................................................

Baud-Rate Generation .............................................................................................................

Data Transmission ..................................................................................................................

FIFO Operation .......................................................................................................................

Interrupts ................................................................................................................................

Loopback Operation ................................................................................................................

Initialization and Configuration .................................................................................................

Register Map ..........................................................................................................................

Register Descriptions ..............................................................................................................

Block Diagram ........................................................................................................................

Functional Description .............................................................................................................

Bit Rate Generation .................................................................................................................

FIFO Operation .......................................................................................................................

Interrupts ................................................................................................................................

Frame Formats .......................................................................................................................

Initialization and Configuration .................................................................................................

Register Map ..........................................................................................................................

Register Descriptions ..............................................................................................................

Block Diagram ........................................................................................................................

Functional Description .............................................................................................................

C Bus Functional Overview ....................................................................................................

Available Speed Modes ...........................................................................................................

Interrupts ................................................................................................................................

Loopback Operation ................................................................................................................

Command Sequence Flow Charts ............................................................................................

Initialization and Configuration .................................................................................................

C Register Map .....................................................................................................................

C Master) ...........................................................................................

Register Descriptions (I2C Slave) .............................................................................................

Block Diagram ........................................................................................................................

Functional Description .............................................................................................................

Internal Reference Programming ..............................................................................................

Initialization and Configuration .................................................................................................

Register Map ..........................................................................................................................

Register Descriptions ..............................................................................................................

217

218

219

220

221

222

254

255

256

263

264

265

291

292

294

295

302

303

304

317

327

329

330

331

12.1

12.2

12.2.1

12.2.2

12.2.3

12.2.4

12.3

12.4

12.5

Synchronous Serial Interface (SSI) ................................................................................ 254

13.1

13.2

13.2.1

13.2.2

13.2.3

13.2.4

13.2.5

13.3

13.4

13.5

13.6

Inter-Integrated Circuit (I

C) Interface ............................................................................ 291

14.1

14.2

14.2.1

14.3

14.4

14.5

Analog Comparators ....................................................................................................... 326

October 01, 2007

Preliminary

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