LM3S315-IRN50-A1T datasheet, PDF

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LM3S315-IRN50-A1T: DescriptionMicrocontroller; File Size2MB，382 Pages; ManufacturerETC2

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P REL I MIN AR Y

LM3S315 Microcontroller

D A TA S H E E T

DS-LM3S31 5-04

Co pyrigh t © 200 7 Lumin ary Micro, In c.

LM3S315 Data Sheet

Table of Contents

Legal Disclaimers and Trademark Information.............................................................................. 2

Revision History ............................................................................................................................. 16

About This Document..................................................................................................................... 18

Audience........................................................................................................................................................... 18

About This Manual............................................................................................................................................ 18

Related Documents .......................................................................................................................................... 18

Documentation Conventions............................................................................................................................. 18

1.1

1.2

1.3

1.4

1.4.1

1.4.2

1.4.3

1.4.4

1.4.5

1.4.6

1.4.7

1.4.8

1.5

Architectural Overview ....................................................................................................... 21

Product Features ................................................................................................................................. 21

Target Applications .............................................................................................................................. 25

High-Level Block Diagram ................................................................................................................... 26

Functional Overview ............................................................................................................................ 27

ARM Cortex™-M3 ............................................................................................................................... 27

Motor Control Peripherals .................................................................................................................... 27

Analog Peripherals .............................................................................................................................. 28

Serial Communications Peripherals..................................................................................................... 28

System Peripherals.............................................................................................................................. 29

Memory Peripherals............................................................................................................................. 30

Additional Features .............................................................................................................................. 30

Hardware Details ................................................................................................................................. 31

System Block Diagram ........................................................................................................................ 32

2.1

2.2

2.2.1

2.2.2

2.2.3

2.2.4

2.2.5

2.2.6

ARM Cortex-M3 Processor Core........................................................................................ 33

Block Diagram ..................................................................................................................................... 34

Functional Description ......................................................................................................................... 34

Serial Wire and JTAG Debug .............................................................................................................. 34

Embedded Trace Macrocell (ETM) ...................................................................................................... 35

Trace Port Interface Unit (TPIU) .......................................................................................................... 35

ROM Table .......................................................................................................................................... 35

Memory Protection Unit (MPU) ............................................................................................................ 35

Nested Vectored Interrupt Controller (NVIC) ....................................................................................... 35

5.1

5.2

5.2.1

5.2.2

5.2.3

5.2.4

5.3

5.4

5.4.1

5.4.2

Memory Map ........................................................................................................................ 41

Interrupts ............................................................................................................................. 43

JTAG Interface .................................................................................................................... 46

Block Diagram ..................................................................................................................................... 47

Functional Description ......................................................................................................................... 47

JTAG Interface Pins............................................................................................................................. 48

JTAG TAP Controller ........................................................................................................................... 49

Shift Registers ..................................................................................................................................... 50

Operational Considerations ................................................................................................................. 50

Initialization and Configuration............................................................................................................. 51

Register Descriptions........................................................................................................................... 52

Instruction Register (IR) ....................................................................................................................... 52

Data Registers ..................................................................................................................................... 54

6.1

6.1.1

System Control.................................................................................................................... 56

Functional Description ......................................................................................................................... 56

Device Identification............................................................................................................................. 56

April 27, 2007

Preliminary

Table of Contents

6.1.2

6.1.3

6.1.4

6.1.5

6.2

6.3

6.4

Reset Control ....................................................................................................................................... 56

Power Control ...................................................................................................................................... 59

Clock Control ....................................................................................................................................... 59

System Control .................................................................................................................................... 61

Initialization and Configuration............................................................................................................. 62

Register Map ....................................................................................................................................... 62

Register Descriptions........................................................................................................................... 63

7.1

7.2

7.2.1

7.2.2

7.3

7.3.1

7.3.2

7.4

7.5

Internal Memory .................................................................................................................. 98

Block Diagram ..................................................................................................................................... 98

Functional Description ......................................................................................................................... 98

SRAM Memory .................................................................................................................................... 98

Flash Memory ...................................................................................................................................... 99

Initialization and Configuration........................................................................................................... 101

Changing Flash Protection Bits ......................................................................................................... 101

Flash Programming ........................................................................................................................... 102

Register Map ..................................................................................................................................... 102

Register Descriptions......................................................................................................................... 103

8.1

8.2

8.2.1

8.2.2

8.2.3

8.2.4

8.2.5

8.2.6

8.3

8.4

8.5

General-Purpose Input/Outputs (GPIOs) ........................................................................ 115

Block Diagram ................................................................................................................................... 116

Functional Description ....................................................................................................................... 117

Data Register Operation .................................................................................................................... 117

Data Direction .................................................................................................................................... 118

Interrupt Operation............................................................................................................................. 118

Mode Control ..................................................................................................................................... 119

Pad Configuration .............................................................................................................................. 119

Identification....................................................................................................................................... 119

Initialization and Configuration........................................................................................................... 119

Register Map ..................................................................................................................................... 121

Register Descriptions......................................................................................................................... 122

9.1

9.2

9.2.1

9.2.2

9.2.3

9.3

9.3.1

9.3.2

9.3.3

9.3.4

9.3.5

9.3.6

9.4

9.5

General-Purpose Timers .................................................................................................. 153

Block Diagram ................................................................................................................................... 154

Functional Description ....................................................................................................................... 154

GPTM Reset Conditions .................................................................................................................... 154

32-Bit Timer Operating Modes........................................................................................................... 154

16-Bit Timer Operating Modes........................................................................................................... 156

Initialization and Configuration........................................................................................................... 160

32-Bit One-Shot/Periodic Timer Mode ............................................................................................... 160

32-Bit Real-Time Clock (RTC) Mode ................................................................................................. 161

16-Bit One-Shot/Periodic Timer Mode ............................................................................................... 161

16-Bit Input Edge Count Mode .......................................................................................................... 161

16-Bit Input Edge Timing Mode ......................................................................................................... 162

16-Bit PWM Mode.............................................................................................................................. 162

Register Map ..................................................................................................................................... 163

Register Descriptions......................................................................................................................... 164

10.

10.1

10.2

Watchdog Timer ................................................................................................................ 185

Block Diagram ................................................................................................................................... 185

Functional Description ....................................................................................................................... 186

Preliminary

April 27, 2007

LM3S315 Data Sheet

10.3

10.4

10.5

Initialization and Configuration........................................................................................................... 186

Register Map ..................................................................................................................................... 186

Register Descriptions......................................................................................................................... 187

11.

11.1

11.2

11.2.1

11.2.2

11.2.3

11.2.4

11.2.5

11.2.6

11.3

11.3.1

11.3.2

11.4

11.5

Analog-to-Digital Converter (ADC) .................................................................................. 208

Block Diagram ................................................................................................................................... 209

Functional Description ....................................................................................................................... 209

Sample Sequencers .......................................................................................................................... 209

Module Control .................................................................................................................................. 210

Hardware Sample Averaging Circuit.................................................................................................. 211

Analog-to-Digital Converter ............................................................................................................... 211

Test Modes ........................................................................................................................................ 211

Internal Temperature Sensor ............................................................................................................. 211

Initialization and Configuration........................................................................................................... 211

Module Initialization ........................................................................................................................... 212

Sample Sequencer Configuration ...................................................................................................... 212

Register Map ..................................................................................................................................... 212

Register Descriptions......................................................................................................................... 213

12.

12.1

12.2

12.2.1

12.2.2

12.2.3

12.2.4

12.2.5

12.2.6

12.3

12.4

12.5

Universal Asynchronous Receivers/Transmitters (UARTs).......................................... 238

Block Diagram ................................................................................................................................... 239

Functional Description ....................................................................................................................... 239

Transmit/Receive Logic ..................................................................................................................... 239

Baud-Rate Generation ....................................................................................................................... 240

Data Transmission ............................................................................................................................. 241

FIFO Operation .................................................................................................................................. 241

Interrupts............................................................................................................................................ 241

Loopback Operation .......................................................................................................................... 242

Initialization and Configuration........................................................................................................... 242

Register Map ..................................................................................................................................... 243

Register Descriptions......................................................................................................................... 244

13.

13.1

13.2

13.2.1

13.2.2

13.2.3

13.2.4

13.3

13.4

13.5

Synchronous Serial Interface (SSI) ................................................................................. 274

Block Diagram ................................................................................................................................... 274

Functional Description ....................................................................................................................... 275

Bit Rate Generation ........................................................................................................................... 275

FIFO Operation .................................................................................................................................. 275

Interrupts............................................................................................................................................ 275

Frame Formats .................................................................................................................................. 276

Initialization and Configuration........................................................................................................... 283

Register Map ..................................................................................................................................... 284

Register Descriptions......................................................................................................................... 285

14.

14.1

14.2

14.2.1

14.3

14.4

14.5

Analog Comparator........................................................................................................... 309

Block Diagram ................................................................................................................................... 309

Functional Description ....................................................................................................................... 309

Internal Reference Programming....................................................................................................... 310

Initialization and Configuration........................................................................................................... 311

Register Map ..................................................................................................................................... 312

Register Descriptions......................................................................................................................... 312

15.

15.1

15.2

Pulse Width Modulator (PWM) ......................................................................................... 320

Block Diagram ................................................................................................................................... 320

Functional Description ....................................................................................................................... 320

April 27, 2007

Preliminary

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