LM3S610-IRN50-B0 datasheet, PDF

Datasheet> All Categories > LM3S610-IRN50-B0

Preview

LM3S610-IRN50-B0: DescriptionMicrocontroller; File Size2MB，409 Pages; ManufacturerETC2

Download Datasheet View All

LM3S610-IRN50-B0 Overview

Microcontroller

Preview

Download Datasheet

View All

P REL I MIN AR Y

LM3S610 Microcontroller

D A TA S H E E T

DS-LM3S61 0-03

Co pyrigh t © 200 7 Lumin ary Micro, In c.

LM3S610 Data Sheet

Table of Contents

Legal Disclaimers and Trademark Information.............................................................................. 2

Revision History ............................................................................................................................. 17

About This Document..................................................................................................................... 19

Audience........................................................................................................................................................... 19

About This Manual............................................................................................................................................ 19

Related Documents .......................................................................................................................................... 19

Documentation Conventions............................................................................................................................. 19

1.1

1.2

1.3

1.4

1.4.1

1.4.2

1.4.3

1.4.4

1.4.5

1.4.6

1.4.7

1.4.8

1.5

Architectural Overview ....................................................................................................... 22

Product Features ................................................................................................................................. 22

Target Applications .............................................................................................................................. 26

High-Level Block Diagram ................................................................................................................... 27

Functional Overview ............................................................................................................................ 28

ARM Cortex™-M3 ............................................................................................................................... 28

Motor Control Peripherals .................................................................................................................... 28

Analog Peripherals .............................................................................................................................. 29

Serial Communications Peripherals..................................................................................................... 29

System Peripherals.............................................................................................................................. 30

Memory Peripherals............................................................................................................................. 31

Additional Features .............................................................................................................................. 31

Hardware Details ................................................................................................................................. 32

System Block Diagram ........................................................................................................................ 33

2.1

2.2

2.2.1

2.2.2

2.2.3

2.2.4

2.2.5

2.2.6

ARM Cortex-M3 Processor Core........................................................................................ 34

Block Diagram ..................................................................................................................................... 35

Functional Description ......................................................................................................................... 35

Serial Wire and JTAG Debug .............................................................................................................. 35

Embedded Trace Macrocell (ETM) ...................................................................................................... 36

Trace Port Interface Unit (TPIU) .......................................................................................................... 36

ROM Table .......................................................................................................................................... 36

Memory Protection Unit (MPU) ............................................................................................................ 36

Nested Vectored Interrupt Controller (NVIC) ....................................................................................... 36

5.1

5.2

5.2.1

5.2.2

5.2.3

5.2.4

5.3

5.4

5.4.1

5.4.2

Memory Map ........................................................................................................................ 42

Interrupts ............................................................................................................................. 44

JTAG Interface .................................................................................................................... 47

Block Diagram ..................................................................................................................................... 48

Functional Description ......................................................................................................................... 48

JTAG Interface Pins............................................................................................................................. 49

JTAG TAP Controller ........................................................................................................................... 50

Shift Registers ..................................................................................................................................... 51

Operational Considerations ................................................................................................................. 51

Initialization and Configuration............................................................................................................. 52

Register Descriptions........................................................................................................................... 53

Instruction Register (IR) ....................................................................................................................... 53

Data Registers ..................................................................................................................................... 55

6.1

6.1.1

System Control.................................................................................................................... 57

Functional Description ......................................................................................................................... 57

Device Identification............................................................................................................................. 57

April 27, 2007

Preliminary

Table of Contents

6.1.2

6.1.3

6.1.4

6.1.5

6.2

6.3

6.4

Reset Control ....................................................................................................................................... 57

Power Control ...................................................................................................................................... 60

Clock Control ....................................................................................................................................... 60

System Control .................................................................................................................................... 62

Initialization and Configuration............................................................................................................. 63

Register Map ....................................................................................................................................... 63

Register Descriptions........................................................................................................................... 64

7.1

7.2

7.2.1

7.2.2

7.3

7.3.1

7.3.2

7.4

7.5

Internal Memory .................................................................................................................. 99

Block Diagram ..................................................................................................................................... 99

Functional Description ......................................................................................................................... 99

SRAM Memory .................................................................................................................................... 99

Flash Memory .................................................................................................................................... 100

Initialization and Configuration........................................................................................................... 102

Changing Flash Protection Bits ......................................................................................................... 102

Flash Programming ........................................................................................................................... 103

Register Map ..................................................................................................................................... 103

Register Descriptions......................................................................................................................... 104

8.1

8.2

8.2.1

8.2.2

8.2.3

8.2.4

8.2.5

8.2.6

8.3

8.4

8.5

General-Purpose Input/Outputs (GPIOs) ........................................................................ 116

Block Diagram ................................................................................................................................... 117

Functional Description ....................................................................................................................... 118

Data Register Operation .................................................................................................................... 118

Data Direction .................................................................................................................................... 119

Interrupt Operation............................................................................................................................. 119

Mode Control ..................................................................................................................................... 120

Pad Configuration .............................................................................................................................. 120

Identification....................................................................................................................................... 120

Initialization and Configuration........................................................................................................... 120

Register Map ..................................................................................................................................... 122

Register Descriptions......................................................................................................................... 123

9.1

9.2

9.2.1

9.2.2

9.2.3

9.3

9.3.1

9.3.2

9.3.3

9.3.4

9.3.5

9.3.6

9.4

9.5

General-Purpose Timers .................................................................................................. 154

Block Diagram ................................................................................................................................... 155

Functional Description ....................................................................................................................... 155

GPTM Reset Conditions .................................................................................................................... 155

32-Bit Timer Operating Modes........................................................................................................... 155

16-Bit Timer Operating Modes........................................................................................................... 157

Initialization and Configuration........................................................................................................... 161

32-Bit One-Shot/Periodic Timer Mode ............................................................................................... 161

32-Bit Real-Time Clock (RTC) Mode ................................................................................................. 162

16-Bit One-Shot/Periodic Timer Mode ............................................................................................... 162

16-Bit Input Edge Count Mode .......................................................................................................... 162

16-Bit Input Edge Timing Mode ......................................................................................................... 163

16-Bit PWM Mode.............................................................................................................................. 163

Register Map ..................................................................................................................................... 164

Register Descriptions......................................................................................................................... 165

10.

10.1

10.2

10.3

Watchdog Timer ................................................................................................................ 186

Block Diagram ................................................................................................................................... 186

Functional Description ....................................................................................................................... 187

Initialization and Configuration........................................................................................................... 187

Preliminary

April 27, 2007

LM3S610 Data Sheet

10.4

10.5

Register Map ..................................................................................................................................... 187

Register Descriptions......................................................................................................................... 188

11.

11.1

11.2

11.2.1

11.2.2

11.2.3

11.2.4

11.2.5

11.2.6

11.3

11.3.1

11.3.2

11.4

11.5

Analog-to-Digital Converter (ADC) .................................................................................. 209

Block Diagram ................................................................................................................................... 209

Functional Description ....................................................................................................................... 210

Sample Sequencers .......................................................................................................................... 210

Module Control .................................................................................................................................. 211

Hardware Sample Averaging Circuit.................................................................................................. 211

Analog-to-Digital Converter ............................................................................................................... 211

Test Modes ........................................................................................................................................ 211

Internal Temperature Sensor ............................................................................................................. 212

Initialization and Configuration........................................................................................................... 212

Module Initialization ........................................................................................................................... 212

Sample Sequencer Configuration ...................................................................................................... 212

Register Map ..................................................................................................................................... 213

Register Descriptions......................................................................................................................... 214

12.

12.1

12.2

12.2.1

12.2.2

12.2.3

12.2.4

12.2.5

12.2.6

12.3

12.4

12.5

Universal Asynchronous Receivers/Transmitters (UARTs).......................................... 239

Block Diagram ................................................................................................................................... 240

Functional Description ....................................................................................................................... 240

Transmit/Receive Logic ..................................................................................................................... 240

Baud-Rate Generation ....................................................................................................................... 241

Data Transmission ............................................................................................................................. 242

FIFO Operation .................................................................................................................................. 242

Interrupts............................................................................................................................................ 242

Loopback Operation .......................................................................................................................... 243

Initialization and Configuration........................................................................................................... 243

Register Map ..................................................................................................................................... 244

Register Descriptions......................................................................................................................... 245

13.

13.1

13.2

13.2.1

13.2.2

13.2.3

13.2.4

13.3

13.4

13.5

Synchronous Serial Interface (SSI) ................................................................................. 275

Block Diagram ................................................................................................................................... 275

Functional Description ....................................................................................................................... 276

Bit Rate Generation ........................................................................................................................... 276

FIFO Operation .................................................................................................................................. 276

Interrupts............................................................................................................................................ 276

Frame Formats .................................................................................................................................. 277

Initialization and Configuration........................................................................................................... 284

Register Map ..................................................................................................................................... 285

Register Descriptions......................................................................................................................... 286

14.

14.1

14.2

14.2.1

14.2.2

14.3

14.4

14.5

14.6

Inter-Integrated Circuit (I2C) Interface ............................................................................ 310

Block Diagram ................................................................................................................................... 310

Functional Description ....................................................................................................................... 310

C Bus Functional Overview ............................................................................................................. 311

Available Speed Modes ..................................................................................................................... 320

Initialization and Configuration........................................................................................................... 321

Register Map ..................................................................................................................................... 322

Register Descriptions (I2C Master).................................................................................................... 322

Register Descriptions (I2C Slave)...................................................................................................... 336

April 27, 2007

Preliminary

Recommended Resources

A differential line driver circuit diagram

Yiyou brand BCD-212H refrigerator circuit

Optocoupler digital display answering machine circuit-a

Alarm type binary password control lock circuit

smoke detector alarm

STK1030 power amplifier circuit

Confused and doubtful: Hello, everyone!I am a worker who has been engaged in vxworks application layer software development for 3 years, doing electric power communication. Now my career plan is to learn the business of ele...; zhaozh2000 Embedded System

Electromagnetic compatibility design of power input port: Abstract: The principle of EMC design at the input end of a switching power supply is analyzed, and specific measures to suppress EMI are proposed based on some practices.Keywords: electromagnetic com...; zbz0529 Power technology

DE0-Nano Development Board Purchase: Who has an unused DE0-Nano development board? Looking to buy it:victory:...; 可不可以滚滚 Buy&Sell

Helper2416-03——Installation of vim under Ubuntu: [align=center][font=Tahoma,][font=楷体, 楷体_GB2312][size=6][color=#0000ff]Installation of vim under Ubuntu[/color][/size][/font][/font][/align] [align=center][font=Tahoma,][color=#ff00][font=楷体, 楷体_GB231...; zhaojun_xf Embedded System

Lessons learned from buying a development board: Lessons learned from buying a development board (forward) Let me talk about my own lessons learned first! The first ARM development board I bought was the 4510-R2 from ** company, which is a developme...; 呱呱 Buy&Sell

O-RAN Testing Tool - Terminal Emulator UEE, Do You Know It?: According to statistics from the Global Mobile Suppliers Alliance (GSA), as of January 2020, 61 commercial 5G networks have been deployed in 34 countries around the world, and 348 operators in 119 cou...; eric_wang Analog electronics

Shortcut: E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF EG EH EI EJ EK EL EM EN EO EP EQ ER ES ET EU EV EW EX EY EZ F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF FG FH FI FJ FK FL FM FN FO FP FQ FR FS FT FU FV FW FX FY FZ G0 G1 G2 G3 G4 G5 G6 G7 G8 G9 GA GB GC GD GE GF GG GH GI GJ GK GL GM GN GO GP GQ GR GS GT GU GV GW GX GZ H0 H1 H2 H3 H4 H5 H6 H7 H8 HA HB HC HD HE HF HG HH HI HJ HK HL HM HN HO HP HQ HR HS HT HU HV HW HX HY HZ I1 I2 I3 I4 I5 I6 I7 IA IB IC ID IE IF IG IH II IK IL IM IN IO IP IQ IR IS IT IU IV IW IX J0 J1 J2 J6 J7 JA JB JC JD JE JF JG JH JJ JK JL JM JN JP JQ JR JS JT JV JW JX JZ K0 K1 K2 K3 K4 K5 K6 K7 K8 K9 KA KB KC KD KE KF KG KH KI KJ KK KL KM KN KO KP KQ KR KS KT KU KV KW KX KY KZ

Popular Components