LM3S8971-IQC20-B0T datasheet, PDF

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LM3S8971-IQC20-B0T: Description32-BIT, FLASH, RISC MICROCONTROLLER, PQFP100; Categorysemiconductor The embedded processor and controller; File Size5MB，577 Pages; ManufacturerETC2

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LM3S8971-IQC20-B0T Overview

32-BIT, FLASH, RISC MICROCONTROLLER, PQFP100

LM3S8971-IQC20-B0T Parametric

Parameter Name	Attribute value
Number of terminals	100
Maximum operating temperature	85 Cel
Maximum supply/operating voltage	2.75 V
Minimum supply/operating voltage	2.25 V
Rated supply voltage	2.5 V
External data bus width	0.0
Number of input and output buses	38
Line speed	50 MHz
Processing package description	GREEN, MS-026BED, LQFP-100
Lead-free	Yes
EU RoHS regulations	Yes
China RoHS regulations	Yes
state	ACTIVE
packaging shape	SQUARE
Package Size	FLATPACK
surface mount	Yes
Terminal form	GULL WING
Terminal spacing	0.5000 mm
terminal coating	TIN
Terminal location	QUAD
Packaging Materials	PLASTIC/EPOXY
Temperature level	INDUSTRIAL
ADC channel	Yes
Address bus width	0.0
Number of digits	32
Maximum FCLK clock frequency	0.0320 MHz
Microprocessor type	RISC MICROCONTROLLER
PWM channel	Yes
ROM programming	FLASH

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LM3S8971 Microcontroller

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LM3S8971 Microcontroller

Table of Contents

About This Document .................................................................................................................... 21

Audience ..............................................................................................................................................

About This Manual ................................................................................................................................

Related Documents ...............................................................................................................................

Documentation Conventions ..................................................................................................................

1.1

1.2

1.3

1.4

1.4.1

1.4.2

1.4.3

1.4.4

1.4.5

1.4.6

1.4.7

1.4.8

Architectural Overview ...................................................................................................... 23

Product Features ......................................................................................................................

Target Applications ....................................................................................................................

High-Level Block Diagram .........................................................................................................

Functional Overview ..................................................................................................................

ARM Cortex™-M3 .....................................................................................................................

Motor Control Peripherals ..........................................................................................................

Analog Peripherals ....................................................................................................................

Serial Communications Peripherals ............................................................................................

System Peripherals ...................................................................................................................

Memory Peripherals ..................................................................................................................

Additional Features ...................................................................................................................

Hardware Details ......................................................................................................................

Block Diagram ..........................................................................................................................

Functional Description ...............................................................................................................

Serial Wire and JTAG Debug .....................................................................................................

Embedded Trace Macrocell (ETM) .............................................................................................

Trace Port Interface Unit (TPIU) .................................................................................................

ROM Table ...............................................................................................................................

Memory Protection Unit (MPU) ...................................................................................................

Nested Vectored Interrupt Controller (NVIC) ................................................................................

2.1

2.2

2.2.1

2.2.2

2.2.3

2.2.4

2.2.5

2.2.6

ARM Cortex-M3 Processor Core ...................................................................................... 37

5.1

5.2

5.2.1

5.2.2

5.2.3

5.2.4

5.3

5.4

5.4.1

5.4.2

Memory Map ....................................................................................................................... 43

Interrupts ............................................................................................................................ 45

JTAG Interface .................................................................................................................... 48

Block Diagram ..........................................................................................................................

Functional Description ...............................................................................................................

JTAG Interface Pins ..................................................................................................................

JTAG TAP Controller .................................................................................................................

Shift Registers ..........................................................................................................................

Operational Considerations ........................................................................................................

Initialization and Configuration ...................................................................................................

Register Descriptions ................................................................................................................

Instruction Register (IR) .............................................................................................................

Data Registers ..........................................................................................................................

6.1

6.1.1

6.1.2

System Control ................................................................................................................... 59

Functional Description ............................................................................................................... 59

Device Identification .................................................................................................................. 59

Reset Control ............................................................................................................................ 59

October 01, 2007

Preliminary

Table of Contents

6.1.3

6.1.4

6.1.5

6.2

6.3

6.4

Power Control ...........................................................................................................................

Clock Control ............................................................................................................................

System Control .........................................................................................................................

Initialization and Configuration ...................................................................................................

Register Map ............................................................................................................................

Register Descriptions ................................................................................................................

Block Diagram ........................................................................................................................

Functional Description .............................................................................................................

Register Access Timing ...........................................................................................................

Clock Source ..........................................................................................................................

Battery Management ...............................................................................................................

Real-Time Clock ......................................................................................................................

Non-Volatile Memory ...............................................................................................................

Power Control .........................................................................................................................

Interrupts and Status ...............................................................................................................

Initialization and Configuration .................................................................................................

Initialization .............................................................................................................................

RTC Match Functionality (No Hibernation) ................................................................................

RTC Match/Wake-Up from Hibernation .....................................................................................

External Wake-Up from Hibernation ..........................................................................................

RTC/External Wake-Up from Hibernation ..................................................................................

Register Map ..........................................................................................................................

Register Descriptions ..............................................................................................................

7.1

7.2

7.2.1

7.2.2

7.2.3

7.2.4

7.2.5

7.2.6

7.2.7

7.3

7.3.1

7.3.2

7.3.3

7.3.4

7.3.5

7.4

7.5

Hibernation Module .......................................................................................................... 117

118

119

120

121

122

123

8.1

8.2

8.2.1

8.2.2

8.3

8.3.1

8.3.2

8.4

8.5

8.6

Internal Memory ............................................................................................................... 136

Block Diagram ........................................................................................................................ 136

Functional Description ............................................................................................................. 136

SRAM Memory ........................................................................................................................ 136

Flash Memory ......................................................................................................................... 137

Flash Memory Initialization and Configuration ........................................................................... 138

Flash Programming ................................................................................................................. 138

Nonvolatile Register Programming ........................................................................................... 139

Register Map .......................................................................................................................... 139

Flash Register Descriptions (Flash Control Offset) ..................................................................... 140

Flash Register Descriptions (System Control Offset) .................................................................. 147

9.1

9.1.1

9.1.2

9.1.3

9.1.4

9.1.5

9.1.6

9.2

9.3

9.4

General-Purpose Input/Outputs (GPIOs) ....................................................................... 160

Functional Description ............................................................................................................. 160

Data Control ........................................................................................................................... 160

Interrupt Control ...................................................................................................................... 161

Mode Control .......................................................................................................................... 162

Commit Control ....................................................................................................................... 162

Pad Control ............................................................................................................................. 162

Identification ........................................................................................................................... 163

Initialization and Configuration ................................................................................................. 163

Register Map .......................................................................................................................... 164

Register Descriptions .............................................................................................................. 166

Preliminary

October 01, 2007

LM3S8971 Microcontroller

10.1

10.2

10.2.1

10.2.2

10.2.3

10.3

10.3.1

10.3.2

10.3.3

10.3.4

10.3.5

10.3.6

10.4

10.5

General-Purpose Timers ................................................................................................. 201

Block Diagram ........................................................................................................................

Functional Description .............................................................................................................

GPTM Reset Conditions ..........................................................................................................

32-Bit Timer Operating Modes ..................................................................................................

16-Bit Timer Operating Modes ..................................................................................................

Initialization and Configuration .................................................................................................

32-Bit One-Shot/Periodic Timer Mode .......................................................................................

32-Bit Real-Time Clock (RTC) Mode .........................................................................................

16-Bit One-Shot/Periodic Timer Mode .......................................................................................

16-Bit Input Edge Count Mode .................................................................................................

16-Bit Input Edge Timing Mode ................................................................................................

16-Bit PWM Mode ...................................................................................................................

Register Map ..........................................................................................................................

Register Descriptions ..............................................................................................................

Block Diagram ........................................................................................................................

Functional Description .............................................................................................................

Initialization and Configuration .................................................................................................

Register Map ..........................................................................................................................

Register Descriptions ..............................................................................................................

202

204

208

209

210

211

212

237

238

239

11.1

11.2

11.3

11.4

11.5

Watchdog Timer ............................................................................................................... 237

12.1

12.2

12.2.1

12.2.2

12.2.3

12.2.4

12.2.5

12.2.6

12.3

12.3.1

12.3.2

12.4

12.5

Analog-to-Digital Converter (ADC) ................................................................................. 260

Block Diagram ........................................................................................................................ 261

Functional Description ............................................................................................................. 261

Sample Sequencers ................................................................................................................ 261

Module Control ........................................................................................................................ 262

Hardware Sample Averaging Circuit ......................................................................................... 263

Analog-to-Digital Converter ...................................................................................................... 263

Test Modes ............................................................................................................................. 263

Internal Temperature Sensor .................................................................................................... 263

Initialization and Configuration ................................................................................................. 264

Module Initialization ................................................................................................................. 264

Sample Sequencer Configuration ............................................................................................. 264

Register Map .......................................................................................................................... 265

Register Descriptions .............................................................................................................. 266

13.1

13.2

13.2.1

13.2.2

13.2.3

13.2.4

13.2.5

13.2.6

13.2.7

13.2.8

13.3

13.4

Universal Asynchronous Receivers/Transmitters (UARTs) ......................................... 293

Block Diagram ........................................................................................................................

Functional Description .............................................................................................................

Transmit/Receive Logic ...........................................................................................................

Baud-Rate Generation .............................................................................................................

Data Transmission ..................................................................................................................

Serial IR (SIR) .........................................................................................................................

FIFO Operation .......................................................................................................................

Interrupts ................................................................................................................................

Loopback Operation ................................................................................................................

IrDA SIR block ........................................................................................................................

Initialization and Configuration .................................................................................................

Register Map ..........................................................................................................................

294

295

296

297

298

299

October 01, 2007

Preliminary

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