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LPC1766
Rev. 00.02 — 12 August 2008
D
32-bit ARM Cortex-M3 microcontroller; 256 kB flash and 64 kB
SRAM with Ethernet, USB 2.0 Host/Device/OTG, CAN, 12-bit
ADC, and 10-bit DAC
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1. General description
The LPC1766 is an ARM Cortex-M3 based microcontroller for embedded applications
featuring a high level of integration and low power consumption. The ARM Cortex-M3 is a
next generation core that offers system enhancements such as enhanced debug features
and a higher level of support block integration.
The LPC1766 operates at CPU frequencies of up to 80 MHz. The ARM Cortex-M3 CPU
incorporates a 3-stage pipeline and uses a Harvard architecture with separate local
instruction and data buses as well as a third bus for peripherals. The ARM Cortex-M3
CPU also includes an internal prefetch unit that supports speculative branching.
The peripheral complement of the LPC1766 includes 256 kB of flash memory, 64 kB of
data memory, Ethernet MAC, USB Device/Host/OTG interface, 8-channel general
purpose DMA controller, 4 UARTs, 2 CAN channels, 2 SSP controllers, SPI interface, 3
I
2
C interfaces, 2-input plus 2-output I
2
S interface, 8 channel 12-bit ADC, 10-bit DAC,
motor control PWM, Quadrature Encoder interface, 4 general purpose timers, 6-output
general purpose PWM, ultra-low power RTC with separate battery supply, and up to 70
general purpose I/O pins.
The LPC1766 is pin-compatible to the LPC2366 ARM7-based microcontroller.
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2. Features
ARM Cortex-M3 processor, running at frequencies of up to 80 MHz. A Memory
Protection Unit (MPU) supporting eight regions is included.
ARM Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC).
256 kB on-chip flash programmimg memory. Enhanced flash memory accelerator
enables high-speed 80 MHz operation with zero wait states.
In-System Programming (ISP) and In-Application Programming (IAP) via on-chip boot
loader software.
64 kB on-chip SRAM includes:
32 kB of SRAM on the CPU with local code/data bus for high-performance CPU
access.
Two 16 kB SRAM blocks with separate access paths for higher throughput. These
SRAM blocks may be used for Ethernet, USB, and DMA memory, as well as for
general purpose CPU instruction and data storage.
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Eight channel General Purpose DMA controller (GPDMA) on the AHB multilayer
matrix that can be used with the SSP, I
2
S, UART, the Analog-to-Digital and
Digital-to-Analog converter peripherals, timer match signals, and for
memory-to-memory transfers.
Multilayer AHB matrix interconnect provides a separate bus for each AHB master.
AHB masters include the CPU, General Purpose DMA controller, Ethernet MAC, and
the USB interface. This interconnect provides communication with no arbitration
delays.
Split APB bus allows high throughput with few stalls between the CPU and DMA.
Serial interfaces:
Ethernet MAC with RMII interface and dedicated DMA controller.
USB 2.0 full-speed device/Host/OTG controller with dedicated DMA controller and
on-chip PHY for device, Host, and OTG functions.
Four UARTs with fractional baud rate generation, internal FIFO, DMA support, and
RS-485 support. One UART has modem control I/O, and one UART has IrDA
support.
CAN 2.0B controller with two channels.
SPI controller with synchronous, serial, full duplex communication and
programmable data length.
Two SSP controllers with FIFO and multi-protocol capabilities. The SSP interfaces
can be used with the GPDMA controller.
Two I
2
C-bus interfaces supporting fast mode with a data rate of 400 kbits/s with
multiple address recognition and monitor mode.
One I
2
C-bus interface supporting full I
2
C-bus specification and fast mode plus with
a data rate of 1 Mbit/s with multiple address recognition and monitor mode.
I
2
S (Inter-IC Sound) interface for digital audio input or output, with fractional rate
control. The I
2
S interface can be used with the GPDMA. The I
2
S interface supports
3-wire and 4-wire data transmit and receive as well as master clock input/output.
Other peripherals:
70 General Purpose I/O (GPIO) pins with configurable pull-up/down resistors and a
new, configurable open-drain operating mode.
12-bit Analog-to-Digital Converter (ADC) with input multiplexing among eight pins,
conversion rates up to 1 MHz, and multiple result registers. The 12-bit ADC can be
used with the GPDMA controller.
10-bit Digital-to-Analog Converter (DAC) with dedicated conversion timer and DMA
support.
Four general purpose timers/counters, with a total of eight capture inputs and ten
compare outputs. Each timer block has an external count input and DMA support.
One motor control PWM with support for three-phase motor control.
Quadrature encoder interface that can monitor one external quadrature encoder.
One standard PWM/timer block with external count input.
Real-Time Clock (RTC) with a separate power domain and dedicated RTC
oscillator. The RTC block includes 64 bytes of battery-powered backup registers.
Watchdog Timer (WDT) resets the microcontroller within a reasonable amount of
time if it enters an erroneous state.
System tick timer, including an external clock input option.
Repetitive interrupt timer provides programmable and repeating timed interrupts.
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© NXP B.V. 2008. All rights reserved.
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Rev. 00.02 — 12 August 2008
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Each peripheral has its own clock divider for further power savings.
Standard JTAG test/debug interface for compatibility with existing tools. Serial Wire
Debug and Serial Wire Trace Port options.
Emulation trace module enables non-intrusive, high-speed real-time tracing of
instruction execution.
Integrated PMU (Power Management Unit) automatically adjusts internal regulators to
minimize power consumption during Sleep, Deep sleep, Power-down, and Deep
power-down modes.
Four reduced power modes: Sleep, Deep-sleep, Power-down, and Deep power-down.
Single 3.3 V power supply (2.4 V to 3.6 V).
Four external interrupt inputs configurable as edge/level sensitive. All pins on PORT0
and PORT2 can be used as edge sensitive interrupt sources.
Non-maskable Interrupt (NMI) input.
Clock output function that can reflect the main oscillator clock, IRC clock, RTC clock,
CPU clock, and the USB clock.
The Wakeup Interrupt Controller (WIC) allows the CPU to automatically wake up from
any priority interrupt that can occur while the clocks are stopped in deep sleep,
power-down, and deep power-down modes.
Processor wake-up from Power-down mode via interrupts from various peripherals.
Brownout detect with separate threshold for interrupt and forced reset.
Power-On Reset (POR).
Crystal oscillator with an operating range of 1 MHz to 24 MHz.
4 MHz internal RC oscillator trimmed to 1 % accuracy that can optionally be used as a
system clock.
PLL allows CPU operation up to the maximum CPU rate without the need for a
high-frequency crystal. May be run from the main oscillator, the internal RC oscillator,
or the RTC oscillator.
USB PLL for added flexibility.
Code Read Protection (CRP) with different security levels.
Available as 100-pin LQFP package (14 x 14 x 1.4 mm).
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3. Applications
eMetering
Lighting
Industrial networking
Alarm systems
White goods
Motor control
4. Ordering information
Table 1.
Ordering information
Package
Name
LPC1766FBD100
LPC1766_0.02
Type number
Description
plastic low profile quad flat package; 100 leads; body 14
×
14
×
1.4 mm
Version
SOT407-1
LQFP100
© NXP B.V. 2008. All rights reserved.
Objective data sheet
Rev. 00.02 — 12 August 2008
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4.1 Ordering options
Table 2.
Ordering options for LPC1766 and related LPC17xx parts
Flash
256 kB
256 kB
128 kB
128 kB
128 kB
64 kB
32 kB
Total
SRAM
64 kB
64 kB
32 kB
32 kB
32 kB
16 kB
8 kB
Ethernet
yes
no
yes
yes
no
no
no
USB
Device/
Host/OTG
Device/
Host/OTG
no
Device/
Host/OTG
Device/
Host/OTG
Device
Device
CAN
2
2
2
2
1
1
1
I
2
S
yes
yes
no
yes
no
no
no
DAC Package
yes
yes
no
yes
yes
no
no
100 pins
100 pins
100 pins
80 pins
80 pins
80 pins
80 pins
Type number
LPC1766FBD100
LPC1765FBD100
LPC1764FBD100
LPC1754FBD80
LPC1753FBD80
LPC1752FBD80
LPC1751FBD80
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Sampling
Q4 2008
Q4 2008
Q4 2008
Q4 2008
Q4 2008
Q4 2008
Q4 2008
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LPC1766_0.02
© NXP B.V. 2008. All rights reserved.
Objective data sheet
Rev. 00.02 — 12 August 2008
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LPC1766
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5. Block diagram
debug
port
JTAG
interface
XTAL1
XTAL2
RESET
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RMII pins
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USB pins
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EMULATION
TRACE MODULE
TEST/DEBUG
INTERFACE
LPC1766
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USB PHY
CLOCK
GENERATION,
POWER CONTROL,
SYSTEM
FUNCTIONS
clocks and
controls
CLKOUT
A
MPU
ARM
CORTEX-M3
I-code
bus
D-code
bus
DMA
CONTROLLER
master
ETHERNET
CONTROLLER
WITH DMA
master
USB HOST/
DEVICE/OTG
CONTROLLER
WITH DMA
master
slave
system
bus
ROM
slave
Multilayer AHB Matrix
slave
SRAM 64 kB
FLASH
ACCELERATOR
FLASH 256 kB
P0 to
P3
HIGH-SPEED
GPIO
slave
slave
AHB TO
APB
BRIDGE 0
slave
AHB TO
APB
BRIDGE 1
SCK1
SSEL1
MISO1
MOSI1
RXD0/TXD0
8
×
UART1
RD1/2
TD1/2
SCL0/1
SDA0/1
SCK/SSEL
MOSI/MISO
2
×
MAT0/1
2
×
CAP0/1
APB slave group 0
SSP1
APB slave group 1
SSP0
SCK0
SSEL0
MISO0
MOSI0
RXD2/3
TXD2/3
3
×
I2SRX
3
×
I2STX
TX_MCLK
RX_MCLK
SCL2
SDA2
4
×
MAT2
2
×
MAT3
2
×
CAP2
2
×
CAP3
EINT[3:0]
UART0/1
CAN1/2
UART2/3
I2S
I2C0/1
SPI0
TIMER 0/1
WDT
I2C2
RI TIMER
TIMER2/3
EXTERNAL INTERRUPTS
SYSTEM CONTROL
PIN CONNECT
MOTOR CONTROL PWM
GPIO INTERRUPT CONTROL
PWM1[7:0]
AD0[7:0]
PWM1
12-bit ADC
MC0A/B
MC1A/B
MC2A/B
MCFB1/2
MCABORT
AOUT
PHA, PHB
INDEX
RTCX1
RTCX2
VBAT
32 kHz
OSCILLATOR
RTC
DAC
QUADRATURE ENCODER
BACKUP REGISTERS
RTC POWER DOMAIN
002aad944
Grey-shaded blocks represent peripherals with connection to the GPDMA.
Fig 1.
LPC1766_0.02
Block diagram
© NXP B.V. 2008. All rights reserved.
Objective data sheet
Rev. 00.02 — 12 August 2008
5 of 70
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