ST24E64
ST25E64
SERIAL EXTENDED ADDRESSING COMPATIBLE
WITH I
2
C BUS 64K (8K x 8) EEPROM
PRELIMINARY DATA
COMPATIBLE with I
2
C EXTENDED
ADDRESSING
TWO WIRE SERIAL INTERFACE,
SUPPORTS 400kHz PROTOCOL
1 MILLION ERASE/WRITE CYCLES, OVER
the FULL SUPPLY VOLTAGE RANGE
40 YEARS DATA RETENTION
SINGLE SUPPLY VOLTAGE
– 4.5V to 5.5V for ST24E64 version
– 2.5V to 5.5V for ST25E64 version
WRITE CONTROL FEATURE
BYTE and PAGE WRITE (up to 32 BYTES)
BYTE, RANDOM and SEQUENTIAL READ
MODES
SELF TIMED PROGRAMING CYCLE
AUTOMATIC ADDRESS INCREMENTING
ENHANCED ESD/LATCH UP
PERFORMANCES
8
1
PSDIP8 (B)
0.25mm Frame
8
1
SO8 (M)
200mil Width
Figure 1. Logic Diagram
VCC
DESCRIPTION
The ST24/25E64 are 64K bit electrically erasable
programmable memories (EEPROM), organized
as 8 blocks of 1024 x 8 bits. The ST25E64 operates
with a power supply value as low as 2.5V. Both
Plastic Dual-in-Line and Plastic Small Outline pack-
ages are available.
3
E0-E2
SCL
WC
ST24E64
ST25E64
SDA
Table 1. Signal Names
E0 - E2
SDA
SCL
WC
V
CC
V
SS
Chip Enable Inputs
Serial Data Address Input/Output
Serial Clock
Write Control
Supply Voltage
Ground
VSS
AI01204B
November 1996
This is preliminary information on a new product now in development or undergoing evaluatio n.Details are subject to change without notice.
1/16
ST24E64, ST25E64
Figure 2A. DIP Pin Connections
Figure 2B. SO Pin Connections
ST24E64
ST25E64
E0
E1
E2
VSS
1
2
3
4
8
7
6
5
AI01205B
ST24E64
ST25E64
VCC
WC
SCL
SDA
E0
E1
E2
VSS
1
2
3
4
8
7
6
5
AI01206C
VCC
WC
SCL
SDA
Table 2. Absolute Maximum Ratings
(1)
Symbol
T
A
T
STG
T
LEAD
V
IO
V
CC
V
ESD
Parameter
Ambient Operating Temperature
Storage Temperature
Lead Temperature, Soldering
Input or Output Voltages
Supply Voltage
Electrostatic Discharge Voltage (Human Body model)
(2)
Electrostatic Discharge Voltage (Machine model)
(3)
(SO8)
(PSDIP8)
40 sec
10 sec
Value
–40 to 125
–65 to 150
215
260
–0.6 to 6.5
–0.3 to 6.5
4000
500
Unit
°C
°C
°C
V
V
V
V
Notes:
1. Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ratings”
may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other
conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum
Rating conditions for extended periods may affect device reliability. Refer also to the SGS-THOMSON SURE Program and
other relevant quality documents.
2. 100pF through 1500Ω; MIL-STD-883C, 3015.7
3. 200pF through 0Ω; EIAJ IC-121 (condition C)
DESCRIPTION
(cont’d)
Each memory is compatible with the I
2
C extended
addressing standard, two wire serial interface
which uses a bi-directional data bus and serial
clock. The ST24/25E64carry a built-in 4 bit, unique
device identification code (1010) corresponding to
the I
2
C bus definition. The ST24/25E64 behave as
slave devices in the I
2
C protocol with all memory
operations synchronized by the serial clock. Read
and write operations are initiated by a START
conditiongenerated by the bus master. The START
condition is followed by a stream of 4 bits (identifi-
cation code 1010), 3 bit Chip Enable input to form
a 7 bit Device Select, plus one read/write bit and
terminated by an acknowledge bit.
2/16
ST24E64, ST25E64
Table 3. Device Select Code
Device Code
Bit
Device Select
Note:
The MSB b7 is sent first.
Chip Enable
b4
0
b3
E2
b2
E1
b1
E0
RW
b0
RW
b7
1
b6
0
b5
1
Table 4. Operating Modes
Mode
Current Address Read
Random Address Read
Sequential Read
Byte Write
Page Write
RW bit
’1’
’0’
’1’
’1’
’0’
’0’
1 to 8192
1
32
Bytes
1
1
Initial Sequence
START, Device Select, RW = ’1’
START, Device Select, RW = ’0’, Address,
reSTART, Device Select, RW = ’1’
As CURRENT or RANDOM Mode
START, Device Select, RW = ’0’
START, Device Select, RW = ’0’
When writing data to the memory it responds to the
8 bits received by asserting an acknowledge bit
during the 9th bit time. When data is read by the
bus master, it acknowledges the receipt of the data
bytes in the same way.
Data transfers are terminated with a STOP condi-
tion. In this way, up to 8 ST24/25E64 may be
connected to the same I
2
C bus and selected indi-
vidually, allowing a total addressing field of 512
Kbit.
Power On Reset: V
CC
lock out write protect.
In
order to prevent data corruption and inadvertent
write operations during power up, a Power On
Reset (POR) circuit is implemented. Untill the V
CC
voltage has reached the POR threshold value, the
internal reset is active: all operations are disabled
and the device will not respond to any command.
In the same way, when V
CC
drops down from the
operating voltage to below the POR threshold
value, all operations are disabled and the device
will not respond to any command. A stable V
CC
must be applied before applying any logic signal.
SIGNALS DESCRIPTION
Serial Clock (SCL).
The SCL input pin is used to
synchronize all data in and out of the memory. A
resistor can be connected from the SCL line to V
CC
to act as a pull up (see Figure 3)
Serial Data (SDA).
The SDA pin is bi-directional
and is used to transfer data in or out of the memory.
It is an open drain output that may be wire-OR’ed
with other open drain or open collector signals on
the bus. Aresistor must be connectedfrom the SDA
bus line to V
CC
to act as pull up (see Figure 3).
Chip Enable (E0 - E2).
These chip enable inputs
are used to set the 3 least significant bits of the 7
bit device select code. They may be driven dynami-
cally or tied to V
CC
or V
SS
to establish the device
select code. Note that the V
IL
and V
IH
levels for the
inputs are CMOS, not TTL compatible.
Write Control (WC).
The Write Control feature
WC is useful to protect the contents of the memory
from any erroneous erase/write cycle. The Write
Control signal is used to enable (WC at V
IH
) or
disable (WC at V
IL
) the internal write protection.
When pin WC is unconnected, the WC input is
internally read as V
IL
(see Table 5).
When WC = ’1’, Device Select and Address bytes
are acknowledged; Data bytes are not acknow-
ledged.
Refer to the AN404 Application Note for more de-
tailed information about Write Control feature.
3/16
ST24E64, ST25E64
Figure 3. Maximum R
L
Value versus Bus Capacitance (C
BUS
) for an I
2
C Bus, f
C
= 400kHz
20
VCC
16
RL
RL max (kΩ)
RL
12
MASTER
8
SDA
SCL
CBUS
CBUS
4
VCC = 5V
0
25
50
CBUS (pF)
75
100
AI01115
DEVICE OPERATION
I
2
C Bus Background
The ST24/25E64support the extended addressing
I
2
C protocol. This protocol defines any device that
sends data onto the bus as a transmitter and any
device that reads the data as a receiver. The device
that controls the data transfer is known as the
master and the other as the slave. The master will
always initiate a data transfer and will provide the
serial clock for synchronisation. The ST24/25E64
are always slave devices in all communications.
Start Condition.
START is identified by a high to
low transition of the SDA line while the clock SCL
is stable in the high state. A START condition must
precede any command for data transfer. Except
during a programming cycle, the ST24/25E64 con-
tinuously monitor the SDA and SCL signals for a
START condition and will not respond unless one
is given.
Stop Condition.
STOPis identified by a low to high
transition of the SDA line while the clock SCL is
stable in the high state. A STOP condition termi-
nates communication between the ST24/25E64
and the bus master. A STOP condition at the end
of a Read command forces the standby state. A
4/16
STOP condition at the end of a Write command
triggers the internal EEPROM write cycle.
Acknowledge Bit (ACK).
An acknowledge signal
is used to indicate a successful data transfer. The
bus transmitter, either master or slave, will release
the SDA bus after sending 8 bits of data. During the
9th clock pulse the receiver pulls the SDA bus low
to acknowledge the receipt of the 8 bits of data.
Data Input.
During data input the ST24/25E64
sample the SDA bus signal on the rising edge of
the clock SCL. For correct device operation the
SDA signal must be stable during the clock low to
high transition and the data must change ONLY
when the SCL line is low.
Device Selection.
To start communication be-
tween the bus master and the slave ST24/25E64,
the master must initiate a START condition. The 8
bits sent after a START condition are made up of a
device select of 4 bits that identifies the device type,
3 Chip Enable bits and one bit for a READ (RW =
1) or WRITE (RW = 0) operation. There are two
modes both for read and write. These are summa-
rised in Table 4 and described hereafter. A commu-
nication between the master and the slave is ended
with a STOP condition.
ST24E64, ST25E64
Table 5. Input Parameters
(1)
(T
A
= 25
°C,
f = 400 kHz )
Symbol
C
IN
C
IN
Z
WCL
Z
WCH
t
LP
Parameter
Input Capacitance (SDA)
Input Capacitance (other pins)
WC Input Impedance
WC Input Impedance
Low-pass filter input time constant
(SDA and SCL)
V
IN
≤
0.3 V
CC
V
IN
≥
0.7 V
CC
5
500
100
Test Condition
Min
Max
8
6
20
Unit
pF
pF
kΩ
kΩ
ns
Note:
1. Sampled only, not 100% tested.
Table 6. DC Characteristics
(T
A
= –40 to 85
°C
or 0 to 70
°C;
V
CC
= 4.5V to 5.5V or 2.5V to 5.5V)
Symbol
I
LI
I
LO
I
CC
Parameter
Input Leakage Current
(SCL, SDA, E0-E2)
Output Leakage Current
Supply Current (ST24 series)
Supply Current (ST25 series)
Supply Current (Standby)
(ST24 series)
Test Condition
0V
≤
V
IN
≤
V
CC
0V
≤
V
OUT
≤
V
CC
SDA in Hi-Z
f
C
= 400kHz
(Rise/Fall time < 30ns)
V
IN
= V
SS
or V
CC
,
V
CC
= 5V
V
IN
= V
SS
or V
CC
,
V
CC
= 5V, f
C
= 400kHz
V
IN
= V
SS
or V
CC
,
V
CC
= 2.5V
V
IN
= V
SS
or V
CC
,
V
CC
= 2.5V, f
C
= 400kHz
–0.3
0.7 V
CC
–0.3
V
CC
– 0.5
I
OL
= 3mA, V
CC
= 5V
I
OL
= 2.1mA, V
CC
= 2.5V
Min
Max
±2
±2
2
1
100
300
5
50
0.3 V
CC
V
CC
+ 1
0.5
V
CC
+ 1
0.4
0.4
Unit
µA
µA
mA
mA
µA
µA
µA
µA
V
V
V
V
V
V
I
CC1
I
CC2
Supply Current (Standby)
(ST25 series)
V
IL
V
IH
V
IL
V
IH
V
OL
Input Low Voltage (SCL, SDA)
Input High Voltage (SCL, SDA)
Input Low Voltage (E0-E2, WC)
Input High Voltage (E0-E2, WC)
Output Low Voltage
Output Low Voltage (ST25 series)
5/16
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