ST24C16, ST25C16
ST24W16, ST25W16
16 Kbit Serial I
2
C Bus EEPROM
with User-Defined Block Write Protection
1 MILLION ERASE/WRITE CYCLES, with
40 YEARS DATA RETENTION
SINGLE SUPPLY VOLTAGE:
– 4.5V to 5.5V for ST24x16 versions
– 2.5V to 5.5V for ST25x16 versions
HARDWARE WRITE CONTROL VERSIONS:
ST24W16 and ST25W16
TWO WIRE SERIAL INTERFACE, FULLY I
2
C
BUS COMPATIBLE
BYTE and MULTIBYTE WRITE (up to 8
BYTES) for the ST24C16
PAGE WRITE (up to 16 BYTES)
BYTE, RANDOM and SEQUENTIAL READ
MODES
SELF TIMED PROGRAMING CYCLE
AUTOMATIC ADDRESS INCREMENTING
ENHANCED ESD/LATCH UP
PERFORMANCES
DESCRIPTION
This specification covers a range of 16 Kbit I
2
C bus
EEPROM products, the ST24/25C16 and the
ST24/25W16. In the text, products are referred to
as ST24/25x16 where "x" is: "C" for Standard ver-
sion and "W" for hardware Write Control version.
The ST24/25x16 are 16 Kbit electrically erasable
programmable memories (EEPROM), organized
as 8 blocks of 256 x8 bits. These are manufactured
in STMicroelectronics’s Hi-Endurance Advanced
CMOS technology which guarantees an endur-
Table 1. Signal Names
PRE
PB0, PB1
SDA
SCL
MODE
WC
V
CC
V
SS
Write Protect Enable
Protect Block Select
Serial Data Address Input/Output
Serial Clock
Multybyte/Page Write Mode
(C version)
Write Control (W version)
Supply Voltage
Ground
Note:
WC signal is only available for ST24/25W16 products.
8
1
PSDIP8 (B)
0.25mm Frame
8
1
SO8 (M)
150mil Width
Figure 1. Logic Diagram
VCC
2
PB0-PB1
PRE
SCL
MODE/WC*
ST24x16
ST25x16
SDA
VSS
AI00866B
February 1999
1/17
ST24/25C16, ST24/25W16
Figure 2A. DIP Pin Connections
Figure 2B. SO8 Pin Connections
ST24x16
ST25x16
PRE
PB0
PB1
VSS
1
2
3
4
8
7
6
5
AI00867B
ST24x16
ST25x16
VCC
MODE/WC
SCL
SDA
PRE
PB0
PB1
VSS
1
2
3
4
8
7
6
5
AI00500B
VCC
MODE/WC
SCL
SDA
Table 2. Absolute Maximum Ratings
(1)
Symbol
T
A
T
STG
T
LEAD
V
IO
V
CC
V
ESD
Parameter
Ambient Operating Temperature
Storage Temperature
Lead Temperature, Soldering
Input or Output Voltages
Supply Voltage
Electrostatic Discharge Voltage (Human Body model)
(2)
Electrostatic Discharge Voltage (Machine model)
(3)
(SO8)
(PSDIP8)
40 sec
10 sec
Value
–40 to 125
–65 to 150
215
260
–0.6 to 6.5
–0.3 to 6.5
4000
500
Unit
°C
°C
°C
V
V
V
V
Notes:
1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings"
may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other
conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum
Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and
other relevant quality documents.
2. 100pF through 1500Ω; MIL-STD-883C, 3015.7
3. 200pF through 0Ω; EIAJ IC-121 (condition C)
DESCRIPTION
(cont’d)
ance of one million erase/write cycles with a data
retention of 40 years. The ST25x16 operates with
a power supply value as low as 2.5V. Both Plastic
Dual-in-Line and Plastic Small Outline packages
are available.
The memories are compatible with the I
2
C stand-
ard, two wire serial interface which uses a bi-direc-
tional data bus and serial clock. The memories
carry a built-in 4 bit, unique device identification
code (1010) corresponding to the I
2
C bus defini-
tion. The memories behave as slave devices in the
I
2
C protocol with all memory operations synchro-
nized by the serial clock. Read and write operations
are initiated by a START condition generated by the
bus master. The START condition is followed by a
stream of 4 bits (identification code 1010), 3 block
select bits, plus one read/write bit and terminated
by an acknowledge bit. When writing data to the
2/17
ST24/25C16, ST24/25W16
Table 3. Device Select Code
Device Code
Bit
Device Select
Note:
The MSB b7 is sent first.
Memory MSB Addresses
b4
0
b3
A10
b2
A9
b1
A8
RW
b0
RW
b7
1
b6
0
b5
1
Table 4. Operating Modes
Mode
Current Address Read
Random Address Read
Sequential Read
Byte Write
Multibyte Write
Page Write
Note:
X = V
IH
or V
IL
.
RW bit
’1’
’0’
’1’
’1’
’0’
’0’
’0’
MODE pin
X
X
X
X
V
IH
V
IL
Bytes
1
1
1 to 2048
1
8
16
Initial Sequence
START, Device Select, RW = ’1’
START, Device Select, RW = ’0’, Address,
reSTART, Device Select, RW = ’1’
As CURRENT or RANDOM Mode
START, Device Select, RW = ’0’
START, Device Select, RW = ’0’
START, Device Select, RW = ’0’
memory it responds to the 8 bits received by as-
serting an acknowledge bit during the 9th bit time.
When data is read by the bus master, it acknow-
ledges the receipt of the data bytes in the same
way. Data transfers are terminated with a STOP
condition.
Data in the 4 upper blocks of the memory may be
write protected. The protected area is programma-
ble to start on any 16 byte boundary. The block in
which the protection starts is selected by the input
pins PB0, PB1. Protection is enabled by setting a
Protect Flag bit when the PRE input pin is driven
High.
Power On Reset: V
CC
lock out write protect.
In
order to prevent data corruption and inadvertent
write operations during power up, a Power On
Reset (POR) circuit is implemented. Untill the V
CC
voltage has reached the POR threshold value, the
internal reset is active: all operations are disabled
and the device will not respond to any command.
In the same way, when V
CC
drops down from the
operating voltage to below the POR threshold
value, all operations are disabled and the device
will not respond to any command. A stable V
CC
must be applied before applying any logic signal.
3/17
ST24/25C16, ST24/25W16
SIGNALS DESCRIPTION
Serial Clock (SCL).
The SCL input signal is used
to synchronise all data in and out of the memory. A
resistor can be connected from the SCL line to V
CC
to act as a pull up (see Figure 3).
Serial Data (SDA).
The SDA signal is bi-directional
and is used to transfer data in or out of the memory.
It is an open drain output that may be wire-OR’ed
with other open drain or open collector signals on
the bus. A resistor must be connected from the SDA
bus line to V
CC
to act as pull up (see Figure 3).
Protected Block Select (PB0, PB1).
PB0 and PB1
input signals select the block in the upper part of
the memory where write protection starts. These
inputs have a CMOS compatible input level.
Protect Enable (PRE).
The PRE input signal, in
addition to the status of the Block Address Pointer
bit (b2, location 7FFh as in Figure 7), sets the PRE
write protection active.
Mode (MODE).
The MODE input is available on pin
7 (see also WC feature) and may be driven dynami-
cally. It must be at V
IL
or V
IH
for the Byte Write
mode, V
IH
for Multibyte Write mode or V
IL
for Page
Write mode. When unconnected, the MODE input
is internally read as V
IH
(Multibyte Write mode).
Write Control (WC).
An hardware Write Control
feature is offered only for ST24W16 and ST25W16
versions on pin 7. This feature is usefull to protect
the contents of the memory from any erroneous
erase/write cycle. The Write Control signal is used
to enable (WC at V
IH
) or disable (WC at V
IL
) the
internal write protection. When unconnected, the
WC input is internally read as V
IL
. The devices with
this Write Control feature no longer supports the
Multibyte Write mode of operation, however all
other write modes are fully supported.
Refer to the AN404 Application Note for more de-
tailed information about Write Control feature.
Figure 3. Maximum R
L
Value versus Bus Capacitance (C
BUS
) for an I
2
C Bus
20
VCC
16
RL
RL
RL max (kΩ)
12
MASTER
8
SDA
SCL
CBUS
CBUS
4
VCC = 5V
0
100
200
CBUS (pF)
300
400
AI01100
4/17
ST24/25C16, ST24/25W16
Table 5. Input Parameters
(1)
(T
A
= 25
°C,
f = 100 kHz )
Symbol
C
IN
C
IN
Z
WCL
Z
WCH
t
LP
Parameter
Input Capacitance (SDA)
Input Capacitance (other pins)
WC Input Impedance (ST24/25W16)
WC Input Impedance (ST24/25W16)
Low-pass filter input time constant
(SDA and SCL)
V
IN
≤
0.3 V
CC
V
IN
≥
0.7 V
CC
5
500
100
Test Condition
Min
Max
8
6
20
Unit
pF
pF
kΩ
kΩ
ns
Note:
1. Sampled only, not 100% tested.
Table 6. DC Characteristics
(T
A
= 0 to 70
°C
or –40 to 85
°C;
V
CC
= 4.5V to 5.5V or 2.5V to 5.5V)
Symbol
I
LI
I
LO
Parameter
Input Leakage Current
Output Leakage Current
Supply Current (ST24 series)
Supply Current (ST25 series)
Supply Current (Standby)
(ST24 series)
Test Condition
0V
≤
V
IN
≤
V
CC
0V
≤
V
OUT
≤
V
CC
SDA in Hi-Z
V
CC
= 5V, f
C
= 100kHz
(Rise/Fall time < 10ns)
V
CC
= 2.5V, f
C
= 100kHz
V
IN
= V
SS
or V
CC
,
V
CC
= 5V
V
IN
= V
SS
or V
CC
,
V
CC
= 5V, f
C
= 100kHz
V
IN
= V
SS
or V
CC
,
V
CC
= 2.5V
V
IN
= V
SS
or V
CC
,
V
CC
= 2.5V, f
C
= 100kHz
–0.3
0.7 V
CC
–0.3
V
CC
– 0.5
I
OL
= 3mA, V
CC
= 5V
I
OL
= 2.1mA, V
CC
= 2.5V
Min
Max
±2
±2
2
1
100
300
5
50
0.3 V
CC
V
CC
+ 1
0.5
V
CC
+ 1
0.4
0.4
Unit
µA
µA
mA
mA
µA
µA
µA
µA
V
V
V
V
V
V
I
CC
I
CC1
I
CC2
Supply Current (Standby)
(ST25 series)
V
IL
V
IH
V
IL
V
IH
V
OL
Input Low Voltage (SCL, SDA)
Input High Voltage (SCL, SDA)
Input Low Voltage
(PB0 - PB1, PRE, MODE, WC)
Input High Voltage
(PB0 - PB1, PRE, MODE, WC)
Output Low Voltage (ST24 series)
Output Low Voltage (ST25 series)
5/17
Analogue and Mixed Signal
京公网安备 11010802033920号
EEWORLD
