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LTC2285CUP-TR

Description
Dual 14-Bit, 125Msps Low Power 3V ADC
File Size577KB,24 Pages
ManufacturerLinear ( ADI )
Websitehttp://www.analog.com/cn/index.html
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LTC2285CUP-TR Overview

Dual 14-Bit, 125Msps Low Power 3V ADC

FEATURES
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LTC2285
Dual 14-Bit, 125Msps
Low Power 3V ADC
DESCRIPTION
The LTC
®
2285 is a 14-bit 125Msps, low power dual 3V
A/D converter designed for digitizing high frequency,
wide dynamic range signals. The LTC2285 is perfect for
demanding imaging and communications applications
with AC performance that includes 72.2dB SNR and 82dB
SFDR for signals at the Nyquist frequency.
Typical DC specs include ±1.5LSB INL, ±0.6LSB DNL. The
transition noise is a low 1.3LSB
RMS
.
A single 3V supply allows low power operation. A separate
output supply allows the outputs to drive 0.5V to 3.6V
logic.
A single-ended CLK input controls converter operation.
An optional clock duty cycle stabilizer allows high perfor-
mance at full speed for a wide range of clock duty cycles.
A data ready output clock (CLKOUT) can be used to latch
the output data.
L,
LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other
trademarks are the property of their respective owners.
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Integrated Dual 14-Bit ADCs
Sample Rate: 125Msps
Single 3V Supply (2.85V to 3.4V)
Low Power: 790mW
72.4dB SNR, 88dB SFDR
110dB Channel Isolation at 100MHz
Flexible Input: 1V
P-P
to 2V
P-P
Range
640MHz Full Power Bandwidth S/H
Clock Duty Cycle Stabilizer
Shutdown and Nap Modes
Data Ready Output Clock
Pin Compatible Family
125Msps: LTC2283 (12-Bit), LTC2285 (14-Bit)
105Msps: LTC2282 (12-Bit), LTC2284 (14-Bit)
80Msps: LTC2294 (12-Bit), LTC2299 (14-Bit)
65Msps: LTC2293 (12-Bit), LTC2298 (14-Bit)
40Msps: LTC2292 (12-Bit), LTC2297 (14-Bit)
64-Pin (9mm × 9mm) QFN Package
APPLICATIONS
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Wireless and Wired Broadband Communication
Imaging Systems
Spectral Analysis
Portable Instrumentation
TYPICAL APPLICATION
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ANALOG
INPUT A
INPUT
S/H
OV
DD
14-BIT
PIPELINED
ADC CORE
OUTPUT
DRIVERS
D13A
D0A
OGND
SNR (dBFS)
SNR vs Input Frequency,
–1dB, 2V Range
75
74
73
72
71
70
69
68
67
66
CLK A
CLOCK/DUTY CYCLE
CONTROL
CLOCK/DUTY CYCLE
CONTROL
OF
MUX
CLK B
CLKOUT
OV
DD
65
0
50
+
ANALOG
INPUT B
INPUT
S/H
14-BIT
PIPELINED
ADC CORE
OUTPUT
DRIVERS
D13B
D0B
OGND
2285 TA01
100 150 200 250 300 350
2285 TA01b
INPUT FREQUENCY (MHz)
2285fb
1

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