ES3207
Video CD/DVD Companion Chip
Product Brief
DESCRIPTION
The ES3207 Video CD/DVD Companion Chip provides an
optimal system design for a Video CD player or a DVD
player.
The ES3207, which is an enhanced version of the pin-
compatible ES3205, integrates most of the required
analog discrete components into a simple, cost-effective
solution and interfaces directly to the ES3210 (Video CD)
or ES3308 (DVD). No glue logic or external microcontroller
is required.
The ES3207 features include a high-quality NTSC/PAL
Digital Video Encoder (DVE), echo, echo reverb,
3DSound, surround sound, video and audio DACs, and a
PLL clock synthesizer. There are three 9-bit video DACs
(one for composite video output and two for S-video
outputs) and two 16-bit sigma-delta audio DACs for
interfacing with current sound systems.
The DVE generates composite and S-video analog
signals. Color Space Conversions (CSC) are provided to
match the input data to the required output format, then
the data is filtered to meet the selected video standards. In
addition, the ES3207 is equipped with a remote control
interface for power on/off, microphone ports, auxiliary
ports, and an interface for accessing internal registers.
Figure 1 shows a block diagram of a typical stand-alone
system using the ES3210 Video CD Processor Chip or the
ES3308 MPEG2 Audio/Video Decoder Chip and an
ES3207 Video CD Companion Chip.
FEATURES
•
Multi-standard TV encoder:
– CCIR601 non-square operation
– NTSC/PAL formats
– Master video mode
– 8-bit interface for YCrCb (4:2:2) input format
– Simultaneous composite and S-video output
– Interlaced operation
•
Audio DACs:
– Two 16-bit sigma-delta DACs
– Accepts I
2
S format data
– Programmable functions
•
•
•
•
•
•
3DSound and surround sound
Remote control interface for power on/off
Digitally controlled echo with up to 168 ms delay
Vocal reverb for theater acoustical effects
Dual microphone input
Clock synthesizer (PLL):
– Based on 27 MHz crystal input
– Generates required clocks for video encoder, audio
DAC, echo and surround sound, and video
processor
•
Device Serial Communication (DSC) port for command
issued/register access
•
Power management
•
100-Pin PQFP
•
Single 5 V power supply
ES3207
Remote
Receiver
CD-ROM
or
DVD-ROM
Drive
ROM
Mic 1
DRAM
VFD
Driver
VFD
Panel
Mic 2
Audio DAC
ES3210
(Video CD)
or
ES3308
(DVD)
DSC
NTSC/PAL Video
PLL
3D/Echo/Surround
Preamp
Volume Control
Preamp
Volume Control
Speakers
Television
Figure 1 ES3207 Video CD Companion Chip System Block Diagram
ESS Technology, Inc.
SAM0076-051701
1
ES3207 VIDEO CD CC PRODUCT BRIEF
PINOUT
PINOUT
PCLK2X
PCLK
VCC
VSS
NC
VSS
XIN
VCC
VSS
XOUT
AUX3
AUX4
AUX5
AUX6
VCC
NC
VDAC
VSSA
VSSA
YDAC
VCCA
VCCA
CDAC
VSSA
VSSA
COMP
RSET
VCM
VREF
VSSA
DSC_D7
HSYNC#
DSC_D6
VSYNC#
DSC_D5
YUV7
YUV6
YUV5
YUV4
VCC
VSS
YUV3
DSC_D4
YUV2
DSC_D3
YUV1
DSC_D2
YUV0
DSC_D1
VSS
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
50
49
48
47
46
45
44
43
42
ES3207
41
40
39
38
37
36
35
34
33
32
31
100
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
VSSA
MIC1
MIC2
AOL
AOR
VCCA
VCCA
VREFP
VREFM
VSSA
AUX15
AUX14
AUX13
RBCK / SER_IN
AUX12
AUX11
AUX10
RSD / SEL_PLL0
VCC
VSS
PIN DESCRIPTION
Name
VSS
VCC
DSC_C
AUX[15:0]
DSC_D[7:0]
DSC_S
DCLK
EXT_CLK
RST#
MUTE
MCLK
TWS
SPLL_OUT
Number
1:2,25:26,29:31,72,75,
77,91,100
3:5,16,32,66,73,78,90
6
40:38,36:34,20,18,14,
67:70,11,9,7
I/O Definition
I
I
I
Ground.
Voltage supply, 5 V.
Clock for programming to access internal registers.
81,83,85,93,95,97,99,8 I/O Data for programming to access internal registers.
10
12
13
15
17
19
I
O
I
I
O
I
I
O
Strobe for programming to access internal registers.
Dual-purpose pin. DCLK is the MPEG decoder clock.
EXT_CLK is the external clock. EXT_CLK is an input during bypass PLL mode.
Video reset (active-low).
Audio mute.
Audio master clock.
Dual-purpose pin. TWS is the transmit audio frame sync.
SPLL_OUT is the select PLL output.
2
SAM0076-051701
VSS
VSS
VCC
VCC
VCC
DSC_C
AUX0
DSC_D0
AUX1
DSC_S
AUX2
DCLK / EXT_CLK
RST#
AUX7
MUTE
VCC
MCLK
AUX8
TWS / SPLL_OUT
AUX9
TSD
TBCK
RWS / SEL_PLL1
RSTOUT#
VSS
VSS
NC
NC
VSS
VSS
I/O Auxiliary control pins.
ESS Technology, Inc.
ES3207 VIDEO CD CC PRODUCT BRIEF
PIN DESCRIPTION
Name
TSD
TBCK
RWS
SEL_PLL1
Number
21
22
23
I/O Definition
I
I
O
I
Transmit audio data input.
Transmit audio bit clock.
Dual-purpose pin. RWS is the receive audio frame sync.
Pins SEL_PLL[1:0] select the PLL clock frequency for the DCLK output.
SEL_PLL1
0
0
1
1
SEL_PLL0
0
1
0
1
DCLK
Bypass PLL (input mode)
27 MHz (output mode)
32.4 MHz (output mode)
40.5 MHz (output mode)
RSTOUT#
NC
RSD
SEL_PLL0
RBCK
SER_IN
VSSA
VREFM
VREFP
VCCA
AOR
AOL
MIC2
MIC1
VREF
VCM
RSET
COMP
CDAC
YDAC
VDAC
XOUT
XIN
PCLK
PCLK2X
HSYNC#
VSYNC#
YUV[7:0]
24
27:28,65:76
O
Reset output (active-low).
No connect. Do not connect to these pins.
O
33
I
O
37
I
Dual-purpose pin. RSD is the receive audio data input.
SEL_PLL0 along with SEL_PLL1 select the PLL clock frequency for the DCLK out-
put. See the table for pin number 23.
Dual-purpose pin. RBCK is the receive audio bit clock.
SER_IN is the serial input DSC mode.
0 = Parallel DSC mode.
1 = Serial DSC mode.
Analog ground.
DAC and ADC minimum reference. Bypass to VCMR with 10
µF
in parallel with 0.1
µF.
DAC and ADC maximum reference. Bypass to VCMR with 10
µF
in parallel with 0.1
µF.
Analog VCC, 5 V.
Right channel output.
Left channel output.
Microphone input 2.
Microphone input 1.
Internal resistor divider generates Common Mode Reference (CMR) voltage.
Bypass to analog ground with 0.1
µF.
ADC Common Mode Reference (CMR) buffer output. CMR is approximately 2.25 V.
Bypass to analog ground with 47
µF
electrolytic in parallel with 0.1
µF.
Full scale DAC current adjustment.
Compensation pin.
Modulated chrominance output.
Y luminance data bus for screen video port.
Composite video output.
Crystal output.
27 MHz crystal input.
41,50:51,56:57,62:63
42
43
44:45,59:60
46
47
48
49
52
53
54
55
58
61
64
71
74
79
80
82
84
86:89,92,94,96,98
I
I
I
I
O
O
I
I
I
I
I
I
O
O
O
O
I
I/O 13.5 MHz pixel clock.
I/O 27 MHz (2 times pixel clock).
O
O
I
Horizontal sync (active-low).
Vertical sync (active-low).
YUV data bus for screen video port.
SAM0076-051701
3
ESS Technology, Inc.
ES3207 VIDEO CD CC PRODUCT BRIEF
MECHANICAL DIMENSIONS
MECHANICAL DIMENSIONS
D
D1
A2
A1
E E1
ES3207
100-Pin PQFP
L
e
b
e1
L1
1
Symbol
D
D1
E
E1
A1
A2
b
e
e1
L
L1
-
-
-
-
-
-
Description
Lead to lead, X-axis
Package’s outside, X-axis
Lead to lead, Y-axis
Package’s outside, Y-axis
Board standoff
Package thickness
Lead width
Lead pitch
Lead gap
Foot length
Lead length
Foot angle
Coplanarity
Leads in X-axis
Leads in Y-axis
Total leads
Package type
Min
23.65
19.90
17.65
13.90
0.10
2.57
0.20
-
0.24
0.65
1.88
0°
-
-
-
-
-
Millimeters
Nom
23.90
20.00
17.90
14.00
0.25
2.71
0.30
0.65
-
0.80
1.95
-
-
30
20
100
PQFP
Max
24.15
20.10
18.15
14.10
0.36
2.87
0.40
-
-
0.95
2.02
7°
0.102
-
-
-
-
No part of this publication may be reproduced, stored in a
retrieval system, transmitted, or translated in any form or
by any means, electronic, mechanical, manual, optical, or
otherwise, without the prior written permission of ESS
Technology, Inc.
ESS Technology, Inc. makes no representations or
warranties regarding the content of this document.
All specifications are subject to change without prior
notice.
ESS Technology, Inc. assumes no responsibility for any
errors contained herein.
(P) U.S. Patent 4,214,125 and others, other patents
pending.
VideoDrive
®
is a registered trademark of ESS Technology,
Inc.
MPEG is the Moving Picture Experts Group of the ISO/IEC.
All other trademarks are owned by their respective
holders and are used for identification purposes only.
4
© 1997 ESS Technology, Inc. All rights reserved.
SAM0076-051701
京公网安备 11010802033920号
EEWORLD
