89H34H16G2ZBBLGI datasheet, PDF

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89H34H16G2ZBBLGI: DescriptionPCI Bus Controller, PBGA1156; CategoryThe embedded processor and controller Microcontrollers and processors; File Size184KB，3 Pages; ManufacturerIDT (Integrated Device Technology); Environmental Compliance

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89H34H16G2ZBBLGI Overview

PCI Bus Controller, PBGA1156

89H34H16G2ZBBLGI Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	IDT (Integrated Device Technology)
package instruction	BGA, BGA1156,34X34,40
Reach Compliance Code	compliant
ECCN code	3A001.A.3
Address bus width
Bus compatibility	I2C; ISA; PCI; SMBUS; VGA
maximum clock frequency	125 MHz
Maximum data transfer rate	34000 MBps
External data bus width
JESD-30 code	S-PBGA-B1156
length	35 mm
Number of terminals	1156
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Encapsulate equivalent code	BGA1156,34X34,40
Package shape	SQUARE
Package form	GRID ARRAY
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	1,2.5,2.5/3.3 V
Certification status	Not Qualified
Maximum seat height	3.42 mm
Maximum slew rate	6264 mA
Maximum supply voltage	1.1 V
Minimum supply voltage	0.9 V
Nominal supply voltage	1 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	35 mm
uPs/uCs/peripheral integrated circuit type	BUS CONTROLLER, PCI

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34-Lane 16-Port PCIe® Gen2

System Interconnect Switch

89HPES34H16G2

Product Brief

The 89HPES34H16G2 is a member of the IDT PRECISE™ family of

PCI Express® switching solutions. The PES34H16G2 is a 34-lane, 16-

port peripheral chip that performs PCI Express packet switching with a

feature set optimized for high-performance applications such as servers,

storage, and communications/networking. It provides connectivity and

switching functions between a PCI Express upstream port and up to

fifteen downstream ports and supports switching between downstream

ports.

Utilizing standard PCI Express Gen2 interconnect, the PES34H16G2

provides the most efficient system interconnect switching solution for

applications requiring high throughput, low latency, and simple board

layout with a minimum number of board layers. Each lane is capable of 5

GT/s of bandwidth in both directions and is fully compliant with PCI

Express Base specification 2.0.

Device Overview

–

Automatic per port link width negotiation

(x8 --> x4 --> x2 --> x1)

–

Crosslink support

–

Automatic lane reversal

–

Autonomous and software managed link width and speed

control

–

Per lane SerDes configuration

• De-emphasis

• Receive equalization

• Drive strength

◆

Switch Partitioning

–

IDT proprietary feature that creates logically independent

switches in the device

–

Supports up to 16 fully independent switch partitions

–

Configurable downstream port device numbering

–

Supports dynamic reconfiguration of switch partitions

• Dynamic port reconfiguration (downstream or upstream)

• Dynamic migration of ports between partitions

• Movable upstream port within and between switch partitions

◆

Initialization / Configuration

–

Supports Root (BIOS, OS, or driver), Serial EEPROM, or

SMBus switch initialization

–

Common switch configurations are supported with pin strap-

ping (no external components)

–

Supports in-system Serial EEPROM initialization/program-

ming

◆

Quality of Service (QoS)

–

Port arbitration

• Round robin

• Weighted Round Robin (WRR)

–

Request metering

• IDT proprietary feature that balances bandwidth among

switch ports for maximum system throughput

–

High performance switch core architecture

• Combined Input Output Queued (CIOQ) switch architecture

with large buffers

◆

Multicast

–

Compliant to the PCI-SIG multicast ECN

–

Supports arbitrary multicasting of Posted transactions

–

Supports 64 multicast groups

–

Multicast overlay mechanism support

–

ECRC regeneration support

◆

Clocking

–

Supports 100 MHz and 125 MHz reference clock frequencies

–

Flexible clocking modes

• Common clock

September 25, 2008

Features

◆

High Performance Non-Blocking Switch Architecture

–

34-lane 16-port PCIe switch

• Three x8 switch ports each of which can bifurcate to two x4

ports (total of six x4 ports)

• Ten x1 switch ports

–

Integrated SerDes supports 5.0 GT/s Gen2 and 2.5 GT/s

Gen1 operation

–

Delivers up to 34 GBps (272 Gbps) of switching capacity

–

Supports 128 Bytes to 2 KB maximum payload size

–

Low latency cut-through architecture

–

Supports one virtual channel and eight traffic classes

◆

Standards and Compatibility

–

PCI Express Base Specification 2.0 compliant

–

Implements the following optional PCI Express features

• Advanced Error Reporting (AER) on all ports

• End-to-End CRC (ECRC)

• Access Control Services (ACS)

• Power Budgeting Enhanced Capability

• Device Serial Number Enhanced Capability

• Sub-System ID and Sub-System Vendor ID Capability

• Internal Error Reporting ECN

• Multicast ECN

• VGA and ISA enable

• L0s and L1 ASPM

• ARI ECN

–

Compatible with IDT 89HPES34H16 PCIe Gen1 switch

◆

Port Configurability

–

x8, x4, and x1 ports

•

Ability to merge adjacent x4 ports to create a x8 port

IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.

1 of 3

2008 Integrated Device Technology, Inc.

89H34H16G2ZBBLGI Related Products

	89H34H16G2ZBBLGI	89H34H16G2ZBBLG	89H34H16G2ZBBLI
Description	PCI Bus Controller, PBGA1156	PCI Bus Controller, PBGA1156	PCI Bus Controller, PBGA1156
Is it Rohs certified?	conform to	conform to	incompatible
Maker	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)
package instruction	BGA, BGA1156,34X34,40	BGA, BGA1156,34X34,40	FCBGA-1156
Reach Compliance Code	compliant	compliant	compliant
ECCN code	3A001.A.3	3A001.A.3	3A001.A.3
Bus compatibility	I2C; ISA; PCI; SMBUS; VGA	I2C; ISA; PCI; SMBUS; VGA	I2C; ISA; PCI; SMBUS; VGA
maximum clock frequency	125 MHz	125 MHz	125 MHz
Maximum data transfer rate	34000 MBps	34000 MBps	34000 MBps
JESD-30 code	S-PBGA-B1156	S-PBGA-B1156	S-PBGA-B1156
length	35 mm	35 mm	35 mm
Number of terminals	1156	1156	1156
Maximum operating temperature	85 °C	70 °C	85 °C
Minimum operating temperature	-40 °C	-	-40 °C
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	BGA	BGA	BGA
Encapsulate equivalent code	BGA1156,34X34,40	BGA1156,34X34,40	BGA1156,34X34,40
Package shape	SQUARE	SQUARE	SQUARE
Package form	GRID ARRAY	GRID ARRAY	GRID ARRAY
Peak Reflow Temperature (Celsius)	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
power supply	1,2.5,2.5/3.3 V	1,2.5,2.5/3.3 V	1,2.5,2.5/3.3 V
Certification status	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	3.42 mm	3.42 mm	3.42 mm
Maximum slew rate	6264 mA	6264 mA	6264 mA
Maximum supply voltage	1.1 V	1.1 V	1.1 V
Minimum supply voltage	0.9 V	0.9 V	0.9 V
Nominal supply voltage	1 V	1 V	1 V
surface mount	YES	YES	YES
technology	CMOS	CMOS	CMOS
Temperature level	INDUSTRIAL	COMMERCIAL	INDUSTRIAL
Terminal form	BALL	BALL	BALL
Terminal pitch	1 mm	1 mm	1 mm
Terminal location	BOTTOM	BOTTOM	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
width	35 mm	35 mm	35 mm
uPs/uCs/peripheral integrated circuit type	BUS CONTROLLER, PCI	BUS CONTROLLER, PCI	BUS CONTROLLER, PCI

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