Freescale Semiconductor
Data Sheet:
Advanced Information
An Energy Efficient Solution by Freescale
Document Number: MC9S08LH64
Rev. 4, 04/2010
MC9S08LH64 Series
Covers: MC9S08LH64 and MC9S08LH36
• 8-Bit HCS08 Central Processor Unit (CPU)
– Up to 40 MHz CPU at 3.6 V to 2.1 V across temperature range
of –40 °C to 85 °C
– Up to 20 MHz at 2.1 V to 1.8 V across temperature range of
–40 °C to 85 °C
– HC08 instruction set with added BGND instruction
– Support for up to 32 interrupt/reset sources
• On-Chip Memory
– Dual array flash read/program/erase over full operating
voltage and temperature
– Random-access memory (RAM)
– Security circuitry to prevent unauthorized access to RAM and
flash contents
• Power-Saving Modes
– Two low-power stop modes
– Reduced-power wait mode
– Low-power run and wait modes allow peripherals to run while
voltage regulator is in standby
– Peripheral clock gating register can disable clocks to unused
modules, thereby reducing currents
– Very low-power external oscillator that can be used in stop2 or
stop3 modes to provide accurate clock source to time-of-day
(TOD) module
– 6
μs
typical wakeup time from stop3 mode
• Clock Source Options
– Oscillator (XOSC) — Loop-control Pierce oscillator; crystal
or ceramic resonator range of 31.25 kHz to 38.4 kHz or 1 MHz
to 16 MHz
– Internal Clock Source (ICS) — Internal clock source module
containing a frequency-locked-loop (FLL) controlled by
internal or external reference; precision trimming of internal
reference allows 0.2% resolution and 2% deviation over
temperature and voltage; supporting bus frequencies from
1 MHz to 20 MHz
• System Protection
– Watchdog computer operating properly (COP) reset with
option to run from dedicated 1 kHz internal clock source or bus
clock
– Low-voltage warning with interrupt
– Low-voltage detection with reset or interrupt
– Illegal opcode detection with reset; illegal address detection
with reset
– Flash block protection
• Development Support
– Single-wire background debug interface
64-LQFP
Case 840F
80-LQFP
Case 917A
– Breakpoint capability to allow single breakpoint setting during
in-circuit debugging (plus two more breakpoints in on-chip
debug module)
– On-chip in-circuit emulator (ICE) debug module containing
three comparators and nine trigger modes
• Peripherals
– LCD — Up to 8×36 or 4×40 LCD driver with internal charge
pump and option to provide an internally-regulated LCD
reference that can be trimmed for contrast control
– ADC —16-bit resolution; with a dedicated differential ADC
input, and 8 single-ended ADC inputs; up to 2.5
μs
conversion
time; hardware averaging; calibration registers, automatic
compare function; temperature sensor; operation in stop3;
fully functional from 3.6 V to 1.8 V
– IIC — Inter-integrated circuit bus module to operate at up to
100 kbps with maximum bus loading; multi-master operation;
programmable slave address; interrupt-driven byte-by-byte
data transfer; broadcast mode; 10-bit addressing
– ACMP — Analog comparator with selectable interrupt on
rising, falling, or either edge of comparator output; compare
option to fixed internal reference voltage; outputs can be
optionally routed to TPM module; operation in stop3
– SCIx — Two full-duplex non-return to zero (NRZ) modules
(SCI1 and SCI2); LIN master extended break generation; LIN
slave extended break detection; wakeup on active edge
– SPI — Full-duplex or single-wire bidirectional;
double-buffered transmit and receive; master or slave mode;
MSB-first or LSB-first shifting
– TPMx — Two 2-channel (TPM1 and TPM2); selectable input
capture, output compare, or buffered edge- or center-aligned
PWM on each channel
– TOD — (Time-of-day) 8-bit, quarter second counter with
match register; external clock source for precise time base,
time-of-day, calendar, or task scheduling functions
– VREFx — Trimmable via an 8-bit register in 0.5 mV steps;
automatically loaded with room temperature value upon reset;
can be enabled to operate in stop3 mode; trim register is not
available in stop modes
• Input/Output
– Dedicated accurate voltage reference output pin, 1.2 V output
(VREFOx); trimmable with 0.5 mV resolution
– Up to 39 GPIOs, two output-only pins
– Hysteresis and configurable pullup device on all input pins;
configurable slew rate and drive strength on all output pins
• Package Options
– 14mm
×
14mm 80-pin LQFP, 10 mm
×
10 mm 64-pin LQFP
© Freescale Semiconductor, Inc., 2009-2010. All rights reserved.
PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE
Contents
1
2
3
Devices in the MC9S08LH64 Series . . . . . . . . . . . . . . . . . . . . 3
Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.2 Parameter Classification. . . . . . . . . . . . . . . . . . . . . . . . . 9
3.3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . 9
3.4 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 10
3.5 ESD Protection and Latch-Up Immunity . . . . . . . . . . . . 11
3.6 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.7 Supply Current Characteristics. . . . . . . . . . . . . . . . . . . 23
3.8 External Oscillator (XOSCVLP) Characteristics . . . . . . 25
3.9 Internal Clock Source (ICS) Characteristics . . . . . . . . . 26
3.10 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.10.1 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.10.2 TPM Module Timing. . . . . . . . . . . . . . . . . . . . . .29
3.10.3 SPI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
3.11 Analog Comparator (ACMP) Electricals . . . . . . . . . . . .33
3.12 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .33
3.13 VREF Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . .40
3.14 LCD Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
3.15 Flash Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . .41
3.16 EMC Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
3.16.1 Radiated Emissions . . . . . . . . . . . . . . . . . . . . . .42
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
4.1 Device Numbering System . . . . . . . . . . . . . . . . . . . . . .42
4.2 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . .43
4.3 Mechanical Drawings . . . . . . . . . . . . . . . . . . . . . . . . . .43
4
•
Revision History
To provide the most up-to-date information, the revision of our documents on the World Wide Web will
be the most current. Your printed copy may be an earlier revision. To verify you have the latest information
available, refer to:
http://freescale.com/
The following revision history table summarizes changes contained in this document.
Rev
1
2
3
4
Date
10/2007
7/2008
1/2009
4/8/2010
Description of Changes
Intial Release of the electrical characteristics in the Reference Manual.
Initial Release after product redefinition and restructuring of information into a separate Data
Sheet and Reference Manual.
Refreshed the draft to include the new VREF module and the latest revisions.
Completed RIDD in the
Table 9;
updated ERREFSTEN in the
Table 10;
changed all V
DDAD
to
V
DDA
, V
SSAD
to V
SSA
; updated the min. of V
REFH
;
Added 64-pin LQFP package information for LH36 MCU; Updated V Room Temp in the
Table 20.
Updated S2I
DD
at V
DD
= 2 and Temp at –40 to 25
°C
Added 64-pin LQFP package for LH36.
Updated ADC data in the
3.12/33
Related Documentation
Find the most current versions of all documents at:
http://www.freescale.com
Reference Manual
—MC9S08LH64RM
Contains extensive product information including modes of operation, memory,
resets and interrupts, register definition, port pins, CPU, and all module
information.
© Freescale Semiconductor, Inc., 2009-2010. All rights reserved.
PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE
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