MPC8555PXAJE datasheet, PDF - EEWORLD Datasheet

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MPC8555PXAJE: Description32-BIT, 667 MHz, RISC PROCESSOR, PBGA783; Categorysemiconductor The embedded processor and controller; File Size1MB，88 Pages; ManufacturerFREESCALE (NXP)

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MPC8555PXAJE Overview

32-BIT, 667 MHz, RISC PROCESSOR, PBGA783

MPC8555PXAJE Parametric

Parameter Name	Attribute value
Number of functions	1
Number of terminals	783
Maximum supply/operating voltage	1.26 V
Minimum supply/operating voltage	1.14 V
Rated supply voltage	1.2 V
External data bus width	64
Line speed	667 MHz
Processing package description	29 × 29 MM, 3.75 MM HEIGHT, 1 MM PITCH, FLIP chip, plastic, BGA-783
state	ACTIVE
Craftsmanship	CMOS
packaging shape	SQUARE
Package Size	GRID array
surface mount	Yes
Terminal form	BALL
Terminal spacing	1 mm
terminal coating	tin lead
Terminal location	BOTTOM
Packaging Materials	Plastic/Epoxy
Address bus width	64
Number of digits	32
boundary scan	Yes
Maximum FCLK clock frequency	166 MHz
floating point unit	Yes
Integrated cache	Yes
low power mode	Yes
Microprocessor type	RISC processor

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Freescale Semiconductor

Technical Data

MPC8555EEC

Rev. 4, 12/2006

MPC8555E PowerQUICC™ III

Integrated Communications Processor

Hardware Specifications

The MPC8555E integrates a PowerPC™ processor core

built on Power Architecture™ technology with system logic

required for networking, telecommunications, and wireless

infrastructure applications. The MPC8555E is a member of

the PowerQUICC™ III family of devices that combine

system-level support for industry-standard interfaces with

processors that implement the embedded category of the

Power Architecture technology. For functional

characteristics of the processor, refer to the

MPC8555E

PowerQUICC™ III Integrated Communications Processor

Reference Manual.

To locate any published errata or updates for this document

refer to http://www.freescale.com or contact your Freescale

sales office.

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Contents

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 8

Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 12

Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . 16

DDR SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Ethernet: Three-Speed, MII Management . . . . . . . . . . 22

Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

CPM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Package and Pin Listings . . . . . . . . . . . . . . . . . . . . . . . 55

Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

System Design Information . . . . . . . . . . . . . . . . . . . . . 77

Document Revision History . . . . . . . . . . . . . . . . . . . . 84

Device Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . 84

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