MSTM-S3-TR
Stratum 3
Timing Module
2111 Comprehensive Drive
Aurora, Illinois 60505
Phone: 630- 851- 4722
Fax: 630- 851- 5040
www.conwin.com
Application
The Connor-Winfield MSTM-S3-TR
Simplified Control Timing Module acts as a
complete system clock module for Stratum 3
timing applications in accordance with GR-
1244, Issue 2 and GR-253, Issue 3.
Connor Winfield’s Stratum 3 timing modules
helps reduce the cost of your design by
minimizing your development time and
maximizing your control of the system clock
with our simplified design.
Features
• 5V Miniature Timing
Module
• Redundant
References
• 2 Synchronous
Outputs Available
From 8 kHz to
77.76MHz
• 40 sec., Filtered,
Hold Over History
• Operational Status
Flags
Bulletin
Page
Revision
Date
Issued By
TM027
1 of 16
P05
02 DEC 02
MBatts
General Description
The Connor-Winfield Stratum 3 Simplified Control Timing Mod-
ule acts as a complete system clock module for general Stratum
3 timing applications. The MSTM is designed to replace similar
units from TF Systems (TF118B) and Raltron (SY0001B).
Full external control input allows for selection and monitoring
of any of four possible operating states: 1) Holdover, 2) External
Reference #1, 3) External Reference #2, and 4) Free Run. Table
#1 illustrates the control signal inputs and corresponding opera-
tional states.
In the absence of External Control Inputs (A,B), the MSTM
enters the Free Run mode and signals an External Alarm. The
MSTM will enter other operating modes upon application of a
proper control signal. Mode 1 operation (A=1, B=0) results in an
output signal that is phase locked to the External Reference
Input #1. Mode 2 operation (A=0, B=1) results in an output sig-
nal that is phase locked to External Reference Input #2. Hold-
over mode operation (A=1, B=1) results in an output signal at or
near the frequency as determined by the latest (last) locked-
signal input values and the holdover performance of the MSTM.
Free Run ModeFree Run mode operation (A=0, B=0) is a guar-
anteed output of 4.6 ppm of the nominal frequency.
Alarm signals are generated at the Alarm Output during Hold-
over and Free Run operation. Alarm Signals are also generated
by Loss-of-Lock and Loss-of-Reference conditions. A high level
indicates an alarm condition. Real-time indication of the opera-
tional mode is available at unique operating mode outputs on
pins 1-4.
Control loop 0.1 Hz filters effectively attenuate any reference
jitter, smooth out phase transients, comply with wander transfer
and jitter tolerances.
Functional Block Diagram
Figure 1
1
Free Run
Ref #1
Ref #2
Hold Over
Free Run
PLL_TVL
Hold Over
Tuning
Voltage
Monitor
Alarm_Out
CNTL A
CNTL B
2
3
4
Holdover
FIFO
Ex Ref 1
Ex Ref 2
Ref
Control
Phase
Build Out
Circuit
LOL & LOR
DPLL
DAC
Stratum3
OCXO
Sync_Out
÷N
Opt_Out*
Reference
Clock
*Only one Opt_Out option is available per module
Function Control Table
Table 1
CNTL
A
0
1
CNTL
B
0
0
Operational
Mode
Free Run (Default Mode)
External
Reference
#1
External
Reference
#2
Normal
PLL_Unlock
LOR
Normal
PLL_Unlock
LOR
Ref 1
0
1
1
0
0
0
0
0
Ref 2
0
0
0
0
1
1
0
0
Hold Over
0
0
0
1
0
0
1
1
Free Run
1
0
0
0
0
0
0
0
PLL Unlock
0
0
1
0
0
1
0
0
Alarm Out
1
0
0
1
0
0
1
1
0
1
1
1
Hold Over
Absolute Maximum Rating
Table 2
Symbol
V
CC
V
I
T
s
Parameter
Power Supply Voltage
Input Voltage
Storage Temperature
Minimum
-0.5
-0.5
-55
Nominal
Maximum
7.0
V
CC
+ 0.5
100
Units
Volts
Volts
deg. C
Notes
1.0
1.0
1.0
Data Sheet #:
TM027
Page 2
of
16
Rev:
P05
Date:
12 / 02 / 02
© Copyright 2001 The Connor-Winfield Corp. All Rights Reserved
Specifications subject to change without notice
Recommended Operating Conditions
Table 3
Symbol
V
cc
V
TH
V
IH
V
IL
t
IN
C
IN
V
OH
V
OL
t
TRANS
Parameter
Power supply voltage
Reset threshold voltage
High level input voltage - TTL
Low level input voltage - TTL
Input signal transition - TTL
Input capacitance
High level output voltage,
I
OH
= -4.0mA, V
CC
= min.
Low level output voltage,
I
OL
= 12.0 mA, V
CC
= min.
Clock output transition time
2.4
Minimum
4.75
4.25
2.0
0
Nominal
5.00
Maximum
5.25
4.5
V
CC
0.8
250
15
5.25
0.4
Units
Volts
Volts
Volts
Volts
ns
pF
Volts
Volts
2.0
Notes
4.0
30
0
70
ns
ns
°C
t
PULSE
T
OP
8kHz input reference pulse
width( positive or negative)
Operating temperature
Specifications
Table 4
Parameter
Frequency Range (Sync_Out)
Frequency Range (Opt_Out)
Supply Current
Timing Reference Inputs
Jitter, Wander and Phase Transient Tolerances
Wander Generation
Wander Transfer
Jitter Generation
Jitter Transfer
Phase Transients
Free Run Accuracy
Hold Over Stability
Inital Offset
Temperature
Drift
Maximum Hold Over History
Pull-in/ Hold-in Range
Lock Time
DPLL Bandwidth
Specifications
8 kHz to 77.76 MHz
8 kHz to 77.76 MHz
250 mA typical, 400 mA during warm-up (Maximum)
8 kHz - 19.44 MHz
GR-1244-CORE 4.2-4.4, GR-253-CORE 5.4.4.3.6
GR-1244-CORE 5.3, GR-253-CORE 5.4.4.3.2
GR-1244-CORE 5.4
GR-1244-CORE 5.5, GR-253-CORE 5.6.2.3
GR-1244-CORE 5.5, GR-253-CORE 5.6.2.1
GR-1244-CORE 5.6, GR-253-CORE 5.4.4.3.3
4.6 ppm over T
OP
±0.37 ppm for initial 24 hrs
±0.05 ppm
±0.28 ppm
±0.04 ppm
40 seconds
±13.8 ppm minimum
30 seconds typical
< 0.1 Hz
5.0
4.0
3.0
Notes
NOTES:
1.0: Stresses beyond those listed under Absolute Maximum Rating may cause damage
to the device. Operation beyond Recommended Conditions is not implied.
2.0:
3.0
Logic is 3.3V CMOS
GR-1244-CORE 3.2.1
4.0:
5.0:
Hold Over stability is the cumulative fractional frequency offset as described by
GR-1244-CORE, 5.2
Pull-in Range is the maximum frequency deviation from nominal clock rate on the
reference inputs to the timing module that can be overcome to pull into synchronization
with the reference
Data Sheet #:
TM027
© Copyright 2001 The Connor-Winfield Corp.
Page 3
of
16
Rev:
P05
Date:
12 / 02 / 02
All Rights Reserved
Specifications subject to change without notice
Pin Description
Table 5
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
Connection
Hold Over
Ref 1
Ref 2
Free Run
GND
Alarm _Out
CNTL A
CNTL B
PLL_Unlock
Tri-State/GND
Sync_Out
GND
Opt_Out
GND
Ex_Ref_2
GND
Ex_Ref_1
Vcc
Description
Indicator output. High output when Hold Over mode is selected by control pins.
Indicator output. High output when Ref 1 mode is selected by control pins.
Indicator output. High output when Ref 2 mode is selected by control pins.
Indicator output. High output when Free Run mode is selected by control pins.
Ground
Alarm output. High output if module is in Free Run, or Hold Over, or LOR.
Mode control input
Mode control input
Indicates that the PLL is not locked to a reference.
0 = Normal operation, 1= Tri-State. Pin is pulled low internally.
Ground pin for normal operation.
Primary timing output signal. Signal is sychronized to reference.
Ground
Secondary output signal. Signal is derived from Sync_Out or from an internal
reference clock depending upon the choosen configuration.
Ground
External Input Reference #2
Ground
External Input Reference #1
+5V dc supply
Ordering Information
MSTM-S3-TR-(Input Reference Frequency)(Opt_Out Frequency)-(Primary Output)
1= 1.544 MHz
2= 2.048 MHz
8= 8 kHz
9= 19.44 MHz
S= Other
Primary Output
÷
N option:
2= 2.048 MHz
8= 8 kHz
N= No output
S= Other
Reference Clock Out option:
6= 16.384 MHz
9= 19.44 MHz
02.048M = 2.048MHz
016.384M = 16.384 MHz
019.44M = 19.44 MHz
032.768M = 32.768 MHz
038.88 M = 38.88 MHz
077.76 M = 77.76 MHz
Example: MSTM-S3-TR-88-038.88M
Data Sheet #:
TM027
Page 4
of
16
Rev:
P05
Date:
12 / 02 / 02
© Copyright 2001 The Connor-Winfield Corp. All Rights Reserved
Specifications subject to change without notice
Typical Application
Figure 2
BITS
System
Signal
Input Select
Line Card 1
A
A
B
MUX
Y
CW’s STM/MSTM module
B
MUX
Y
S
CW’s SCG
2000/4000
Clock out
S
RCV
Timing Card #N
A
A
B
MUX
Y
CW’s STM/MSTM module
MUX
B
Line Card N
S
CW’s SCG
2000/4000
Clock out
Y
S
RCV
System Select
Typical System Test Set-up
Figure 3
G P S or LO R AN
T im in g S o u r c e
T h is d e v ic e s u p p lie s s y s te m tim e
in f o r m a t io n . It c a n b e th o u g h t o f a s
s u p p ly in g " a b s o lu te tim e " r e fe r e n c e
in f o r m a t io n
S a m p le M T IE D a t a fo r S T M -S 3 /M S T M - S 3
1 .0 E - 6
10
MHz
M T IE (s
P o s s ib le C h o i c e s In c lu d e
S ta n fo r d R e s e a r c h M o d e l: F S 7 0 0
T r u e tim e M o d e l X X X
T y p i c a l r e s p o n s e - 3 0 0 0 s e c o n d t e s t - J it t e r a p p li e d ( 2 U I @
re f d a t e A P R
k dh
2 2 1 99 8
1 0 H z)
1 0 0 .0 E - 9
1 0 .0 E - 9
M T IE
1 2 4 4 - 5 .2 M a s k ( A )
1 2 4 4 - 5 .2 M a s k ( B )
1 2 4 4 - 5 .6 M a s k
G R 2 5 3 - 5 . 4 . 4 .3 . 2
1 .0 E - 9
1 0 0 .0 E - 3
1 .0 E + 0
1 0 .0 E + 0
1 0 0 .0 E + 0
1 .0 E + 3
1 0 .0 E + 3
O b s e r v a t io n T im e ( s )
C o p y ri g h t
1 9 9 8 C o n n o r - W in f i e ld a l l r i g h t s re s e r v e d
T a rg e t S y s te m U n d e r T e s t
E x te r n a l
R e fe re n c e
In p u t
A r b it r a r y
W a v e fo r m
G e n e ra to r
D S 1 r a te R Z ( 1 .5 4 4 M H z ) , E 1 r a te R Z o r 8 k H z
c lo c k R Z w ith n o is e m o d u la tio n
C lo c k o r B IT S lo g ic le v e l
c lo c k in p u t ( T T L , C M O S ,
e tc .)
S ta n d a r d s
C o m p lia n c e
D o c u m e n ts
M T IE , T D E V , W a n d e r T r a n s f e r ,
a n d W a n d e r G e n e r a t io n P l o t s
OC-12 Line Card
OC-48 Line Card
OC-3 Line Card
DS-1 Line Card
Timing Card
Timing Card
Line Card
S a m p le W a n d e r G e n e r a t io n (T D E V ) f o r S T M /M S T M - S 3
1 .0 E - 6
Noise Modulation Input
T y p i c a l r e s p o n s e - 3 0 0 0 s e c o n d te s t - J itt e r a p p l ie d ( 2 U I @
re f d a te A P R
k dh
2 2 1 99 8
10 H z)
10
MHz
1 0 0 .0 E - 9
. . . . ...
1 0 .0 E - 9
TDE V (s e c
T D EV
1 .0 E - 9
G R 1 2 4 4 - F ig 5 . 1
G R 1 2 4 4 - F ig 5 - 3
E x te r n a l
R e fe re n c e
In p u t
A r b it r a r y
W a v e fo r m
G e n e ra to r
[N o is e
S o u rc e ]
1 0 0 .0 E - 1 2
1 0 .0 E - 3
1 0 0 .0 E - 3
1 .0 E + 0
1 0 .0 E + 0
1 0 0 .0 E + 0
1 .0 E + 3
In te g r a t io n
T im e
(s e c )
C o p y r i g h t 1 9 9 8 C o n n o r - W i n f ie l d a ll l rig h t s r e s e r v e d
D S 1 r a te [1 .5 4 4 M H z ] B IT S B ip o la r
D S - 1 , O C - 3 , O C - 1 2 e le c tr ic a l o r o p tic a l s ig n a ls
10
MHz
T e k tr o n ix
S J300E
10
MHz
T im e - s ta m p e d e n s e m b le
b a s e d o n a b s o lu te tim e
r e fe r e n c e ( 1 0 M H z in p u t)
P h a s e E r r o r d a ta o u t p u t
E x te r n a l
R e fe re n c e
In p u t
HP 53310A
M o d u la tio n A n a ly z e r / T im e I n te r v a l A n a ly z e r
W a n d e r A n a ly z e r d a ta ( IE E E - 4 8 8 )
E x te r n a l
R e fe re n c e
In p u t
T E K T R O N IX S J 3 0 0 E
IE E E - 4 8 8 C o n tr o lle r
P la t f o r m f o r s o f tw a r e
H P 5 3 3 0 5 A P h a s e A n a ly z e r
H P E 1748A S ync
M e a s u re m e n t
T e k t r o n ix W a n d e r A n a ly z e r
Data Sheet #:
TM027
© Copyright 2001 The Connor-Winfield Corp.
Page 5
of
16
Rev:
P05
Date:
12 / 02 / 02
All Rights Reserved
Specifications subject to change without notice
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