MYSON
TECHNOLOGY
MTP805
(Rev. 0.9)
8051 Embedded USB/PS2 Keyboard/Mouse
Controller
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
8051 core, 6MHz operating frequency.
256-byte RAM, 8K-byte program Flash-ROM.
Compliant with Low Speed USB Spec.1.1 including 3 Endpoints: one is Control endpoint (8-byte IN & 8-
byte OUT FIFOs), the other two are Interrupt endpoints (8-byte IN FIFOs).
Built-in 3.3V regulator for USB Interface.
Suspend / Resume operation.
Idle and Power down mode wake-up by interrupt.
8 dedicated Key scan input pins and 18/19 Key scan output pins.
Built-in low power reset circuit and Watchdog timer.
PS2 compatible mouse interface.
PS2 compatible keyboard interface share with USB interface.
CPU clock can be double by S/W setting.
40-pin DIP, 42-pin SDIP or 44-pin PLCC package.
GENERAL DESCRIPTIONS
The MTP805 micro-controller is an 8051 CPU core embedded device specially tailored to USB/PS2
Keyboard/Mouse applications. It includes an 8051 CPU core, 256-byte SRAM, Low Speed USB Interface
and an 8K-byte internal program Flash-ROM.
BLOCK DIAGRAM
KSO0~7
KSO8~15
MSDATA
MSCLK
PS2CLK
PS2DATA
P1.0~7
P2.0~7
P3.0
P3.1
P3.4
P3.5
XCVR
V33
DP
DM
8051
WDT
SIE
OSC2
OSC1
RESET
P0.0~7
P3.7
P3.6
ALE
P3.2
P3.3
DBUS
/RD
/WR
ALE
/INT0
/INT1
XFR
KSO16~17
GPIO0~1
KSI0~7
LED0~2
GPO0
This datasheet contains new product information. Myson Technology reserves the rights to modify the product specification without
notice. No liability is assumed as a result of the use of this product. No rights under any patent accompany the sale of the product.
Revision 0.9
-1-
2000/07/19
MYSON
TECHNOLOGY
PIN CONNECTION
MTP805
(Rev. 0.9)
VSS
OSC1
OSC2
RST
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
MTP805
40 Pin
PDIP #1
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
DP/PS2CLK
DM/PS2DATA
V33
VDD
LED0
LED1
LED2
MSCLK
MSDATA
GPIO0
KSO17
KSO16
KSO15
KSO14
KSO13
KSO12
KSO11
KSO10
KSO9
KSO8
VSS
OSC1
OSC2
RST
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
MTP805
40 Pin
PDIP #2
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
DP/PS2CLK
DM/PS2DATA
V33
VDD
LED0
LED1
LED2
GPO0
MSCLK
MSDATA
KSO17
KSO16
KSO15
KSO14
KSO13
KSO12
KSO11
KSO10
KSO9
KSO8
NC
VDD
V33
DM/PS2DATA
DP/PS2CLK
VSS
OSC1
OSC2
RST
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
MTP805
42 Pin
SDIP
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
DP/PS2CLK
DM/PS2DATA
V33
VDD
LED0
LED1
LED2
GPO0
MSCLK
MSDATA
GPIO1
GPIO0
KSO17
KSO16
KSO15
KSO14
KSO13
KSO12
KSO11
KSO10
KSO9
OSC2
RST
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
7
8
9
10
11
12
13
14
15
16
17
MTP805
44 Pin
PLCC
VSS
OSC1
40
41
42
43
44
1
2
3
4
5
6
39
38
37
36
35
34
33
32
31
30
29
LED0
LED1
LED2
GPO0
MSCLK
MSDATA
GPIO1
GPIO0
KSO17
KSO16
KSO15
28
27
26
25
24
23
22
21
20
19
18
KSO9
KSO8
KSO7
KSO6
KSO5
NC
KSO14
KSO13
KSO12
KSO11
KSO10
Revision 0.9
-2-
2000/07/19
MYSON
TECHNOLOGY
PIN DESCRIPTION
Name
VSS
OSC1
OSC2
RST
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17
GPIO0
GPIO1
MSDATA
MSCLK
GPO0
LED2
LED1
LED0
VDD
V33
DM/PS2DATA
DP/PS2CLK
Type
-
I
O
I
I
I
I
I
I
I
I
I
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
-
O
I/O
I/O
Description
MTP805
(Rev. 0.9)
Ground.
Oscillator input.
Oscillator output.
Active high reset. (with internal pull-down resistor)
Key scan input 0. (Schmitt-trigger with 10K/33K/50K pull-up resistor)
Key scan input 1. (Schmitt-trigger with 10K/33K/50K pull-up resistor)
Key scan input 2. (Schmitt-trigger with 10K/33K/50K pull-up resistor)
Key scan input 3. (Schmitt-trigger with 10K/33K/50K pull-up resistor)
Key scan input 4. (Schmitt-trigger with 10K/33K/50K pull-up resistor)
Key scan input 5. (Schmitt-trigger with 10K/33K/50K pull-up resistor)
Key scan input 6. (Schmitt-trigger with 10K/33K/50K pull-up resistor)
Key scan input 7. (Schmitt-trigger with 10K/33K/50K pull-up resistor)
Key scan output 0 (8051’ P1.0). (Pseudo open-drain)
s
Key scan output 1 (8051’ P1.1). (Pseudo open-drain)
s
Key scan output 2 (8051’ P1.2). (Pseudo open-drain)
s
Key scan output 3 (8051’ P1.3). (Pseudo open-drain)
s
Key scan output 4 (8051’ P1.4). (Pseudo open-drain)
s
Key scan output 5 (8051’ P1.5). (Pseudo open-drain)
s
Key scan output 6 (8051’ P1.6). (Pseudo open-drain)
s
Key scan output 7 (8051’ P1.7). (Pseudo open-drain)
s
Key scan output 8 (8051’ P2.0). (Pseudo open-drain)
s
Key scan output 9 (8051’ P2.1). (Pseudo open-drain)
s
Key scan output 10 (8051’ P2.2). (Pseudo open-drain)
s
Key scan output 11 (8051’ P2.3). (Pseudo open-drain)
s
Key scan output 12 (8051’ P2.4). (Pseudo open-drain)
s
Key scan output 13 (8051’ P2.5). (Pseudo open-drain)
s
Key scan output 14 (8051’ P2.6). (Pseudo open-drain)
s
Key scan output 15 (8051’ P2.7). (Pseudo open-drain)
s
Key scan output 16. (Pseudo open-drain)
Key scan output 17. (Pseudo open-drain)
General purpose I/O 0. (Pseudo open-drain)
General purpose I/O 1. (Pseudo open-drain)
Mouse data (8051’ P3.0). (Pseudo open-drain)
s
Mouse clock (8051’ P3.1). (Pseudo open-drain)
s
General purpose output 0. (Open-drain with 420 ohm serial resistor)
Output pin to drive LED 2. (Open-drain with 420 ohm serial resistor)
Output pin to drive LED 1. (Open-drain with 420 ohm serial resistor)
Output pin to drive LED 0. (Open-drain with 420 ohm serial resistor)
Positive Power Supply.
3.3 Volt USB regulator output. (Must connect to 1uF or larger capacitor)
USB DM / PS2 keyboard data (8051’ P3.5).
s
USB DP / PS2 keyboard clock (8051’ P3.4).
s
“Pseudo open-drain” pin is 8051 Port1’ standard. It can sink at least 4mA current when output low level, and
s
drive at least 4mA current for 2 X’ cycle when output transit from low to high, then keep drive 100uA to
tal
maintain the pin at high level.
Revision 0.9
-3-
2000/07/19
MYSON
TECHNOLOGY
FUNCTIONAL DESCRIPTIONS
1. 8051 CPU Core
MTP805
(Rev. 0.9)
MTP805 includes all 8051 functions with the following exceptions:
1.1 PSEN, ALE, #RD and #WR pins are disabled. The external RAM access is restricted to XFRs within the
MTP805.
1.2 Port0, port3.2, port3.3, port3.6 and port3.7 are not general-purpose I/O ports. They are dedicated to
special application.
1.3 #INT0 and #INT1 input pin is not provided, it is connected to special interrupt sources.
1.4 UART and Timer1 are not supported.
Note: All registers listed in this document reside in external RAM area (XFR). For internal RAM memory map
please refer to 8051 spec.
2. Memory Allocation
2.1 Internal Special Function Registers (SFR)
The SFR is a group of registers that are the same as standard 8051.
2.2 Internal RAM
There are total 256 bytes internal RAM in MTP805, same as standard 8052.
2.3 External Special Function Registers (XFR)
The XFR is a group of registers allocated in the 8051 external RAM area 00h - 2Fh. Most of the registers are
used for USB function. Program can initialize Ri value and use "MOVX" instruction to access these registers.
FFh
Internal RAM
Accessible by
indirect
addressing only
(Using
MOV A,@Ri
instruction)
SFR
Accessible by
direct addressing
80h
7Fh
Internal RAM
Accessible by
direct and indirect
addressing
2Fh
XFR
Accessible by
indirect external
RAM addressing
(Using
MOVX A,@Ri
instruction
00h
00h
Revision 0.9
-4-
2000/07/19
MYSON
TECHNOLOGY
3. I/O Pin Usage
MTP805
(Rev. 0.9)
3.1 KSO0~7
These pins are direct output from the 8051’ Port1 and dedicated for key scan output. The pin’ input
s
s
function is removed. Read 8051’ Port1 is only read the data in the Port1’ output register. These pins are
s
s
“Pseudo open-drain” structure.
3.2 KSO8~15
These pins are direct output from the 8051’ Port2 and dedicated for key scan output. The pin’ input
s
s
function is removed. Read 8051’ Port2 is only read the data in the Port2’ output register. These pins are
s
s
“Pseudo open-drain” structure.
4mA
50uA
500uA
Read
Data
2 OSC
period
delay
D
Write
Data
/WR
Output
Register
CK
Q
Pin
4mA
KSO0~15
3.3 KSO16~17, GPIO0~1
These pins are output from MTP805’ XFR. They can be used as key scan output or general purpose I/O.
s
Read these pins will read the data on pin. These pins are also “Pseudo open-drain” structure.
4mA
50uA
500uA
1 OSC
period
delay
D
Write
Data
/WR
Output
Register
CK
Q
4mA
Read
Data
Pin
KSO16~17, GPIO0~1
3.4 MSCLK, MSDATA
These pins are connected to 8051’ P3.1 and P3.0. The usage of these pins are the same as standard 8051
s
except the UART’ function being not provided. These pins are also “Pseudo open-drain” structure.
s
Read
Latch
Data
2 OSC
period
delay
D
Write
Data
/WR
Output
Register
CK
Q
4mA
50uA
500uA
Pin
4mA
Read
Pin
Data
MSCLK, MSDATA
Revision 0.9
-5-
2000/07/19
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