Nm9715
PCI Dual 1284 Printer Ports
Features
•
Single 5V operation
•
Low power
•
Pin-to-pin compatible to Nm9705
•
PCI compatible dual 1284 printer port
•
Multi-mode compatible controller (SPP, PS2, EPP,
ECP)
•
Fast data rates up to 1.5 Mbytes/s (parallel port)
•
Re-map function for legacy ports
•
16-byte FIFO (parallel)
•
Microsoft Windows compatible registers
•
Software programmable mode selects
•
128-pin QFP package
Applications
•
Printer server
•
Portable backup units
•
Printer interface
•
Add-on I/O cards
Application Notes
•
AN-9715
General Description
The Nm9715 is a dual 1284 parallel port controller with
PCI bus interface. Nm9715 fully supports the existing
Centronics printer interface as well as PS/2, EPP, and
ECP modes.
The Nm9715 is ideally suited for PC applications, such
as high speed parallel ports. The Nm9715 is available
in a 128-pin QFP package. It is fabricated using an ad-
vanced submicron CMOS process to achieve low drain
power and high speed requirements.
Ordering Information
Commercial Grade
Nm9715CV
128-QFP
0° C to +70° C
MosChip Semiconductor
♦
3335 Kifer Rd, Santa Clara, CA 95051
♦
Tel (408) 737-7141
♦
Fax (408) 737-7708
Nm9715
PCI Dual 1284 Printer Ports
Nm9715 Block Diagram
PDA0 - PDA7
1284
Parallel Port-A
CLK
nRESET
AD0 - AD31
nFRAME, nIRDY
nLOCK, IDSEL,
nTRDY, nSTOP,
nDEVSEL,
nPARR,nSERR
nC/BE0, nC/BE1,
nC/BE3, nC/BE4
FAULT-A, SLCT-A, PE-A
nACK-A, nBUSY-A
nSTROBE-A, nAUTOFDX-A
INIT-A, nSLCTIN-A
P
C
I
I
N
T
E
R
F
A
C
E
P
C
I
B
R
I
D
G
E
1284
Parallel Port-B
PDB0 - PDB7
FAULT-B, SLCT-B, PE-B
nACK-B, nBUSY-B
nSTROBE-B, nAUTOFDX-B
INIT-B, nSLCTIN-B
nINTA
PCI Clk
EEprom
Interface
EE-CLK
EE-CS
EE-DO
Page 2
EE-EN
EE-DI
Rev. 1.2
Nm9715
PCI Dual 1284 Printer Ports
128-Pin QFP Package
nRESET
EE-CLK
EE-DO
EE-CS
EE-EN
nINTA
EE-DI
AD29
128
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
AD30
127
AD31
126
GND
GND
GND
125
VCC
VCC
N.C.
N.C.
124
CLK
122
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
123
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
VCC
AD28
AD27
AD26
AD25
AD24
GND
nC/BE3
IDSEL
VCC
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
VCC
GND
GND
nC/BE2
nFRAME
nIRDY
nTRDY
nDEVSEL
nSTOP
nLOCK
nPERR
nSERR
PAR
nC/BE1
GND
AD15
AD14
AD13
AD12
AD11
N.C.
N.C.
N.C.
GND
PA7
PA6
PA5
PA4
GND
PA3
PA2
PA1
PA0
VCC
GND
PEA
nACKA
nBUSYA
SLCTA
nFAULTA
VCC
nSTROBEA
nAUTOFDA
nINITA
nSLCTINA
GND
nSTROBEB
nAUTOFDB
nINITB
nSLCTINB
nFAULTB
nACKB
nBUSYB
PEB
SLCTB
N.C.
VCC
N.C.
Nm9715CV
VCC
AD10
AD9
AD8
nC/BE0
GND
GND
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
VCC
N.C.
N.C.
N.C.
N.C.
N.C.
GND
N.C.
N.C.
N.C.
N.C.
Rev. 1.2
Page 3
Nm9715
PCI Dual 1284 Printer Ports
Pin Name
nRESET
128
121
Type
I
Description
PCI system reset (active low). Resets all internal register, sequencers, and
signals to a consistent state. During reset condition, AD31-0 and nSER are
three-stated.
Multiplexed PCI address/data bus. A bus transaction consists of an address
phase followed by one or more data phases. During the address phase AD31-
0 contain a physical address. Write data is stable and valid when nIRDY and
nTRDY are asserted (active).
See AD31-29 description.
See AD31-29 description.
See AD31-29 description.
See AD31-29 description.
See AD31-29 description.
Frame is driven by the current master to indicate the beginning and duration
of an access. nFRAME is asserted to indicate a bus transaction is beginning.
While nFRAME is active, data transfer continues.
Initiator Ready. During a write, nIRDY asserted indicates that the initiator is
driving valid data onto the data bus. During a read, nIRDY asserted indicates
that the initiator is ready to accept data from the Nm9715.
Target Ready (three-state). It is asserted when Nm9715 is ready to complete
the current data phase.
Nm9715 asserts nSTOP to indicate that it wishes the initiator to stop the
transaction in process on the current data phase.
Lock indicates an atomic operation that may require multiple transactions to
complete.
Initialization Device Select. It is used as a chip select during configuration
read and write transactions.
Device Select (three-state). Nm9715 asserts nDEVSEL when the Nm9715
has decoded its address.
Parity Error (three-state). Is used to report parity errors during all PCI trans-
actions except a special cycle. The minimum duration of nPERR is one clock
cycle.
AD31-29 126-128
I/O
AD28-24
AD23-16
AD15-11
AD10-8
AD7-0
nFRAME
2-6
11-18
34-38
40-42
46-53
23
I/O
I/O
I/O
I/O
I/O
I
nIRDY
24
I
nTRDY
25
O
nSTOP
27
O
nLOCK
28
I
IDSEL
9
I
nDEVSEL
26
O
nPERR
29
O
Page 4
Rev. 1.2
Nm9715
PCI Dual 1284 Printer Ports
Pin Name
nSERR
128
30
Type
O
Description
System Error (open drain). This pin goes low when address parity errors are
detected.
Even Parity. Parity is even parity across AD31-0 and nC/BE3-0. PAR is stable
and valid one clock after the address phase. For data phase, PAR is stable
and valid one clock after either nIRDY is asserted on a write transaction, or
nTRDY is asserted on a read transaction.
Bus Command and Byte Enable. During the address phase of a transaction,
nC/BE3-0 defines the bus command. During data phase, nC/BE3-0 are used
as byte enables. nC/BE3 applies to byte “3”.
Bus Command and Byte Enable. During the address phase of a transaction,
nC/BE3-0 defines the bus command. During data phase, nC/BE3-0 are used
as byte enables. nC/BE2 applies to byte “2”.
Bus Command and Byte Enable. During the address phase of a transaction,
nC/BE3-0 defines the bus command. During data phase, nC/BE3-0 are used
as byte enables. nC/BE1 applies to byte “1”.
Bus Command and Byte Enable. During the address phase of a transaction,
nC/BE3-0 defines the bus command. During data phase, nC/BE3-0 are used
as byte enables. nC/BE0 applies to byte “0”.
PCI active low interrupt output (open-drain). This signal goes low (active)
when an interrupt condition occurs.
External EEprom chip select (active high). After power on reset, Nm9715
reads the EEprom and loads the read-only configuration registers sequen-
tially from the first 64 bytes in the EEprom.
External EEprom clock.
External EEprom data input.
External EEprom data output.
Enable/Disable external EEprom (active high, internal pull-up). External
EEprom can be disabled when this pin is tied to GND or pulled low. When
external EEprom is disabled, the default values for Nm9715 will be loaded
into PCI configuration register.
PAR
31
I/O
nC/BE3
8
I
nC/BE2
22
I
nC/BE1
32
I
nC/BE0
43
I
nINTA
120
O
EE-CS
115
O
EE-CLK
EE-DI
EE-DO
EE-EN
116
118
117
123
O
I
O
I
SLCTB
SLCTA
68
84
I
Peripheral/printer selected (internal pull-up). This pin is set to high by periph-
eral/printer when it is selected.
Rev. 1.2
Page 5
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