EEWORLDEEWORLDEEWORLD

Part Number

Search

D-SUB-205AE23BANDBF1

Description
D Type Connector, 23 Contact(s), Female, 0.109 inch Pitch, Solder Terminal, M3, Plug
CategoryThe connector    The connector   
File Size124KB,1 Pages
ManufacturerPalPilot
Environmental Compliance
Download Datasheet Parametric View All

D-SUB-205AE23BANDBF1 Overview

D Type Connector, 23 Contact(s), Female, 0.109 inch Pitch, Solder Terminal, M3, Plug

D-SUB-205AE23BANDBF1 Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerPalPilot
Reach Compliance Codecompliant
ECCN codeEAR99
Other featuresROHS COMPLIANT
body width0.492 inch
subject depth0.492 inch
body length1.98 inch
Body/casing typePLUG
Contact to complete cooperationGOLD (5) OVER NICKEL (50)
Contact completed and terminatedTin (Sn) - with Nickel (Ni) barrier
Contact point genderFEMALE
Contact materialCOPPER ALLOY
contact modeSTAGGERED
Contact resistance15 mΩ
Contact styleRND PIN-SKT
Dielectric withstand voltage1000VAC V
Insulation resistance3000000000 Ω
Insulator colorWHITE
insulator materialPOLYBUTYLENE TEREPHTHALATE
JESD-609 codee3
Manufacturer's serial number205
Plug contact pitch0.109 inch
Match contact row spacing0.112 inch
Installation option 1M3
Installation option 2RIVET
Installation methodRIGHT ANGLE
Installation typeBOARD
PCB row number2
Number of rows loaded2
Maximum operating temperature105 °C
Minimum operating temperature-55 °C
PCB contact patternSTAGGERED
PCB contact row spacing2.8448 mm
Plating thickness5u inch
Rated current (signal)3 A
GuidelineUL
reliabilityCOMMERCIAL
Shell surfaceNICKEL
Shell materialSTEEL
Terminal length0.125 inch
Terminal pitch2.7686 mm
Termination typeSOLDER
Total number of contacts23
How to evaluate the low power consumption of FPGA?
Recently, everyone is analyzing the data on FPGA low power consumption.I'll join in the fun,Let’s discuss with you how to define low power consumption of FPGA.To be honest, I didn’t pay much attention...
wstt FPGA/CPLD
Analysis of the "Signal" topic in the National College Student Electronics Contest
1. Previous " Signal Source " Competition Topics In the 11th National Undergraduate Electronic Design Competition, there were only five signal source questions [ 1] : ①Signal Generator (8th session , ...
宋元浩 Electronics Design Contest
Matlab Lesson 4 - Polynomial Arrays
Setting ranges and drawing! [[i] This post was last edited by gaoxiao on 2009-6-12 14:20 [/i]]...
gaoxiao Microcontroller MCU
Xilinx clock management
Hello everyone! How do you manage the clock in ise?...
applelonger FPGA/CPLD
Find the right solution
Hello everyone, I am looking for an ARM solution, Ubuntu system, CPU can be 6410 or other, need a full set of information, preferably a ready-made solution, which can be used with a little modificatio...
tryagain1 Linux and Android
I have just started learning Cadence Virtuoso and found that as long as the schematic diagram appears in the parallel inductor simulation, an error will be reported.
I have just started learning Cadence Virtuoso, and I found that whenever there is a parallel inductor simulation in the schematic diagram, it will report an error that the parallel inductor forms a sh...
非标准理工男 Analog electronics

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 794  762  2926  916  1028  16  59  19  21  20 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号