Product Data Sheet
FX-101
Frequency Translator
Output frequencies up to 77.760 MHz
Locked to specified Input frequency, e.g. 8 kHz
1" x 0.8" x 0.2", Surface Mount (FR4 base)
Single 5.0 Vdc or 3.3 Vdc supply
Optional CMOS or PECL Output
Low Output Jitter
SONET / SDH / ATM / DSL-PON interconnects
8 kHz/16.384 MHz/19.44 MHz to 77.76 MHz
8 kHz/1.544 MHz/2.048 MHz to 44.736MHz
FX-101
Lock Detect
VCXO Monitor
TriState Enable/Disable
Input
Frequency
Frequency
Divider
Phase Freq
Detector
Loop Filter
VCXO
PECL IC
or Buffer
Frequency
Divider
Frequency
Select
Microprocessor
Vectron's FX-101 is a crystal based frequency translator which is used to translate any input
frequency such as 8 kHz, 1.544 MHz, 2.048 MHz, 19.440 MHz etc. to any specific frequency less
than or equal to 77.76 MHz. The input frequency does not have to be a 50/50% duty cycle and as
an example can be an 8 kHz signal with a logic high "on time" of only 1us, such as a BITS clock.
The FX-101 also has the ability to translate up to any of 4 different input frequencies to one
common output frequency, such as input frequencies of 8 kHz and 1.544 MHz and 19.44 MHz and
any other frequency between 333 Hz and 77.76 MHz translating them to an output frequency up
to 77.76 MHz.
The "Input Frequency tracking capability" is the total amount of input frequency deviation in which
the FX-101 is guaranteed to track or translate. As an example, a typical input clock would be
8 kHz ± 20 ppm. The FX-101 is guaranteed to track at least ±50 ppm of error over temperature/
aging/ power supply and is more than twice what most applications require. The PLL control
voltage is brought out through a 470K ohm resistor. This would allow for the use of external
circuitry (analog comparators or an A/D converter plus a processor) to detect when the control
voltage is getting close to the limits of the pull range.
Supply Voltage,
Supply Current
Input Signal,
0
Input Signal,
1
OUTPUT,
V
OH
V
OL
C
= 5 Vdc
D
= 3.3 Vdc
A
= HCMOS
A
= HCMOS
F
= Comp PECL
V
DD
V
DD
I
DD
CLKIN
CLKIN
---
V
OH
V
OL
t
R
/t
F
---
V
OH
V
OL
t
R
/t
F
Sym
Sym
4.75
3.15
0
0.7(V
DD)
---
V
DD
-1.025
V
DD
-1.810
5.00
3.30
45
5.25
3.45
70
0.2(V
DD)
5.5
Vdc
Vdc
mA
Vdc
Vdc
---
Vdc
Vdc
ns
---
Vdc
Vdc
ns
%
%
ps
ppm
PECL
---
V
DD
-0.880
V
DD
-1.620
Rise / Fall Time
(77.76 MHz)
OUTPUT,
V
OH
,
V
OL
,
A
= HCMOS
I
OL
= 50 uA
I
OL
= 50 uA
0.5
---
V
DD
-0.3
HCMOS
2
---
0.1
Rise / Fall Time
(
77.76 MHz/20% to 80%)
Output Symmetry,
Freq >62.208 MHz and 3.3V
Jitter @ 77.76 MHz
(rms 12 kHz to 20 MHz)
Input Frequency Tracking Capability
(Can translate a Stratum 1,2,3,3E,4
or SONET Min source)
Operating Temperature
Size
1.4
45
40
0.5
2.5
55
60
1.0
APR
+/-50
Temp Range
C
=
0º to +70º
C
C
Temp Range
F
= -40º to +85º
C
C
See page 3 for outline Drawings and Dimensions
mm
(in)
5.08
(0.20)
17.78
(0.70)
2.54
(0.10)
1.01
(0.040)
3.81
(0.15)
1.73
(0.068)
1.73
(0.068)
20.32
(0.80)
25.4
(1.00)
1
2
3
CLKIN
GND
LD
(Output)
Logic "1" indicates a locked condition and requires a couple hundred pF capacitor to ground to
operate correctly.
Logic "0" indicates that no input signal is detected and can be used as a loss-of-signal alarm.
Toggles when not locked.
Under locked conditions, should be >0.3V and <3.0 V for the 3.3 volt option or >0.5V and <4.5V
for the 5 volt option. Input frequency may be out of range if voltage exceeds these limits.
Input Frequency
Ground
Lock Detect
4
5
6
7
8
Monitor
(Output)
NC
NC
GND
Tri-state
(Input)
Disable
(Input)
PLL/ VCXO control voltage
No Connection
No Connection
Ground
TriState (HCMOS
output option)
Logic "1" (or no connect) = Output enabled
Logic "0" = Output in high impedance
Logic "1" = Output disabled
Logic "0" (or no connect) = Output enabled
Disable (PECL
output option)
9
10
11
12
13
14
15
16
OUT
COUT
NC
Select A
Select B
NC
GND
V
DD
VCXO Output (PECL) or HCMOS Output
Complementary VCXO Output (PECL) or NC for HCMOS output option
No Connection
Do not Exceed Vdd
(NC for one input frequency)
Do not Exceed Vdd
(NC for one or two input frequencies)
No Connection
Ground
Power Supply Voltage (5 Vdc or 3.3 Vdc)
mm
(in)
2.54
(0.10)
1.91
(0.075)
3.04
(0.12)
19.05
(0.75)
9.53
(0.375)
8.89
(0.35)
17.78
(0.70)
Temperature ( º
C)
pre-heating
60 to 90 sec.
@ 140º to 160º
C
C
reflow
40 to 60 sec.
@ >183º
C
NOTE:
This FX-101 should not be subjected to a wash process that will immerse it in solvents.
NO CLEAN is the recommended procedure.
V
DD
f1
f2
f3
f4
8 kHz
13.00 MHz
19.44 MHz
38.88 MHz
*
74LS151
Multiplexer
(MUX)
(16)
*
Lock Detect
VCXO Monitor
*
(3)
(4)
(8)
(9)
(Fin)
(1)
Input
Frequency
FX-101
TriState Enable/Disable
Frequency
Divider
Phase Freq
Detector
Loop Filter
VCXO
PECL IC
or Buffer
B
Frequency
Select
Microprocessor
Frequency
Divider
77.76 MHz
(Fout)
A (12/13)
Input
Freq.
f1
f2
f3
f4
Select
A B
0 0
0 1
1 0
1 1
(2,7,15)
=
=
=
=
A B
bypass capacitors; 10 uF, ferrite bead, 0.1 uF and a 100pF
capacitor would be typical.
*Note:
VI highly recommends either a linear regulator or
All components outside the dotted line box are user supplied components and/or connections. This is just one possible
configuration of the FX-101. For additional information about your specific needs please contact our Factory.
FAQ
s
Q: What are the different input frequencies Available?
A: The FX-101 is able to handle any input frequency between 333 Hz and 77.76 MHz.
(A list of standard frequencies is available on page 7.)
Q: How many different input frequencies can a specific FX-101 accept?
A: Each FX-101 can be programmed to accept up to 4 different frequencies.
Q: Does the output frequency need to be 77.76 MHz?
A: No, the output frequency can be any frequency between 1.024 MHz and 77.76 MHz.
(A list of standard frequencies is available on page 7.)
Q: If there is only one input pin, how can your unit accept 4 different frequencies?
A: The customer is required to supply a multiplexer which would switch between the
different input frequencies. The multiplexersselect pins would need to be sync to
d
the select pins of the FX-101. (The drawing above illustrates this configuration.)
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