Preliminary
K4S281633D-RL(N)
CMOS SDRAM
8Mx16
SDRAM 54CSP
(V
DD
/V
DDQ
3.0V/3.0V & 3.3V/3.3V)
Revision 0.6
November 2001
Rev. 0.6 Nov. 2001
Preliminary
K4S281633D-RL(N)
Revision History
Revision 0.0 (February 21. 2001, Target)
CMOS SDRAM
• First generation of 128Mb Low Power SDRAM without special function (V
DD
3.0V, V
DDQ
3.0V)
Revision 0.1 (June 4. 2001, Target)
• Addition of DC Current value.
Revision 0.2 (June 20. 2001, Target)
• Changed device name from low power sdram to mobile dram.
Revision 0.3 (August 1. 2001, Target)
• Change of tSAC from 6ns to 6.5ns in case of -1L part, from 7ns to 7.5ns in case of -15 part.
• Change of tOH from 3ns to 3.5ns.
• Change V
IH
min. from 2.0 V to 0.8xV
DDQ
and V
OH
min. from 2.4V to 0.9xV
DDQ.
Revision 0.4 (October 6. 2001, Preliminary)
• Changed DC current.
• Changed of CL2 tSAC from 6ns to 7ns and CL3 tSAC from 6.5ns to 7ns for -75 part.
• Changed of CL2 tSAC from 6.5ns to 8ns and CL1 tSAC from 18ns to 20ns for -1L part.
• Changed of tOH from 3ns to 2.5ns.
• Changed of tSS from 2.5ns to 2.0ns for -75 part and from 3.0ns to 2.5ns for -1L part.
• Integration of VDDQ 1.8V device and 2.5V device.
• Changed VIH min. from 0.8xVDDQ to 0.9xVDDQ and VOH min. from 0.9xVDDQ to 0.95xVDDQ.
• Changed VIL max. from 0.8V to 0.3V and VOL min. from 0.4V to 0.2V.
• Changed IOH from -0.1mA to -2mA and IOL from 0.1mA to 2mA.
• Erased -15 bin and added -1H bin.
Revision 0.5 (October 12. 2001, Preliminary)
• Changed VIH min. from 0.9xVDDQ to 2.0V and VOH min. from 0.95xVDDQ to 2.4V.
• Changed VIL max. from 0.3V to 0.8V and VOL min. from 0.2V to 0.4V.
Revision 0.6 (November 7. 2001, Preliminary)
• Changed VIH min. from 2.0V to 2.2V and VIL max. from 0.8V to 0.5V.
Rev. 0.6 Nov. 2001
Preliminary
K4S281633D-RL(N)
2M x 16Bit x 4 Banks SDRAM in 54CSP
FEATURES
• 3.0V & 3.3V power supply.
• LVTTL compatible with multiplexed address.
• Four banks operation.
• MRS cycle with address key programs.
-. CAS latency (1 & 2 & 3).
-. Burst length (1, 2, 4, 8 & Full page).
-. Burst type (Sequential & Interleave).
• All inputs are sampled at the positive going edge of the system
clock.
• Burst read single-bit write operation..
• DQM for masking.
• Auto refresh.
• 64ms refresh period (4K cycle).
• Commercial Temperature Operation (-25°C ~ 70
°C).
Extended Temperature Operation (-25°C ~ 85°C).
K4S281633D-RL/N75
K4S281633D-RL/N1H
CMOS SDRAM
GENERAL DESCRIPTION
The K4S281633D is 134,217,728 bits synchronous high data
rate Dynamic RAM organized as 4 x 2,097,152 words by 16
bits, fabricated with SAMSUNG′s high performance CMOS
technology. Synchronous design allows precise cycle control
with the use of system clock and I/O transactions are possible
on every clock cycle. Range of operating frequencies, program-
mable burst length and programmable latencies allow the same
device to be useful for a variety of high bandwidth, high perfor-
mance memory system applications.
ORDERING INFORMATION
Part No.
Max Freq.
133MHz(CL=3)
100MHz(CL=2)
100MHz(CL=2)
*1
Interface Package
LVTTL
54 CSP
K4S281633D-RL/N1L 100MHz(CL=3)
-RN ; Low Power, Operating Temperature : -25’C~85’C.
-RL ; Low Power, Operating Temperature : -25’C~70’C.
FUNCTIONAL BLOCK DIAGRAM
Note :
1. In case of 40MHz Frequency, CL1 can be supported.
I/O Control
LWE
Data Input Register
LDQM
Bank Select
2M x 16
Sense AMP
2M x 16
2M x 16
2M x 16
Refresh Counter
Output Buffer
Row Decoder
Row Buffer
DQi
Address Register
CLK
ADD
Column Decoder
Col. Buffer
Latency & Burst Length
LRAS
LCBR
LCKE
LRAS
LCBR
LWE
LCAS
Programming Register
LWCBR
LDQM
Timing Register
CLK
CKE
CS
RAS
CAS
WE
LDQM
UDQM
* Samsung Electronics reserves the right to change products or specification without notice.
Rev. 0.6 Nov. 2001
Preliminary
K4S281633D-RL(N)
Package Dimension and Pin Configuration
< Bottom View
*1
>
E
1
CMOS SDRAM
< Top View
*2
>
54Ball(6x9) CSP
9
A
B
C
D
1
D
E
F
G
H
J
8
7
6
5
4
3
2
1
e
1
A
B
C
D
E
F
G
H
J
D/2
D
2
DQ15
DQ13
DQ11
DQ9
NC
CLK
A11
A7
A5
3
V
SSQ
V
DDQ
V
SSQ
V
DDQ
V
SS
CKE
A9
A6
A4
7
V
DDQ
V
SSQ
V
DDQ
V
SSQ
V
D D
CAS
BA0
A0
A3
8
DQ0
DQ2
DQ4
DQ6
LDQM
RAS
BA1
A1
A2
9
V
D D
DQ1
DQ3
DQ5
DQ7
WE
CS
A10
V
D D
V
SS
DQ14
DQ12
DQ10
DQ8
UDQM
NC
A8
V
SS
E
E/2
Pin Name
CLK
Pin Function
System Clock
Chip Select
Clock Enable
Address
Bank Select Address
Row Address Strobe
Column Address Strobe
Write Enable
Data Input/Output Mask
Data Input/Output
Power Supply/Ground
Data Output Power/Ground
*2: Top View
CS
CKE
A
0
~ A
11
A
A1
BA
0
~ BA
1
RAS
CAS
WE
L(U)DQM
DQ
0
~
15
V
DD
/V
SS
V
DDQ
/V
SSQ
Max. 0.20
Encapsulant
ϕ
b
ζ
*1: Bottom View
< Top View
*2
>
#A1 Ball Origin Indicator
SAMSUNG
WEEK
K4S281633D-RL(N)
[Unit:mm]
Symbol
A
A
1
E
E
1
D
D
1
e
ϕb
ζ
Min
0.90
0.30
-
-
-
-
-
0.40
-
Typ
0.95
0.35
8.00
6.40
8.00
6.40
0.80
0.45
-
Max
1.00
0.40
-
-
-
-
-
0.50
0.08
Rev. 0.6 Nov. 2001
Preliminary
K4S281633D-RL(N)
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to Vss
Voltage on V
D D
supply relative to Vss
Storage temperature
Power dissipation
Short circuit current
Symbol
V
I N
, V
OUT
V
DD
, V
DDQ
T
STG
P
D
I
OS
Value
-1.0 ~ 4.6
-1.0 ~ 4.6
-55 ~ +150
1
50
CMOS SDRAM
Unit
V
V
°C
W
mA
Note :
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS
Recommended operating conditions (Voltage referenced to V
SS
= 0V, T =-25°C ~ 70
°C
(Commercial), -25
°C
~ 85°C (Extended))
A
Parameter
Supply voltage
Input logic high voltage
Input logic low voltage
Output logic high voltage
Output logic low voltage
Input leakage current
Symbol
V
D D
V
DDQ
V
I H
V
IL
V
O H
V
OL
I
LI
Min
2.7
2.7
2.2
-0.3
2.4
-
-10
Typ
3.0
3.0
3.0
0
-
-
-
Max
3.6
3.6
V
DDQ
+0.3
0.5
-
0.4
10
Unit
V
V
V
V
V
V
uA
1
2
I
O H
= -2mA
I
OL
= 2mA
3
Note
Note
:
1. V
IH
(max) = 5.3V AC. The overshoot voltage duration is
≤
3ns.
2. V
IL
(min) = -2.0V AC. The undershoot voltage duration is
≤
3ns.
3. Any input 0V
≤
V
IN
≤
V
DDQ
.
Input leakage currents include HI-Z output leakage for all bi-directional buffers with Tri-State outputs.
4. Dout is disabled, 0V
≤
V
OUT
≤
V
DDQ.
CAPACITANCE
Clock
(V
DD
= 3.0V, T
A
= 23°C, f = 1MHz, V
REF
=0.9V
±
50 mV)
Pin
Symbol
C
CLK
C
IN
C
ADD
C
OUT
Min
2.0
2.0
2.0
3.5
Max
4.0
4.0
4.0
6.0
Unit
pF
pF
pF
pF
Note
RAS, CAS, WE, CS, CKE, DQM
Address
D Q
0
~ DQ
15
Rev. 0.6 Nov. 2001
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