SPT7734
8-BIT, 40 MSPS,175 mW A/D CONVERTER
FEATURES
•
•
•
•
•
•
•
•
•
•
Monolithic 40 MSPS Converter
175 mW Power Dissipation
On-Chip Track-and-Hold
Single +5 V Power Supply
TTL/CMOS Outputs
5 pF Input Capacitance
Low Cost
Tri-State Output Buffers
High ESD Protection: 3,500 V Minimum
Selectable +3 V or +5 V Logic I/O
APPLICATIONS
• All High-Speed Applications Where
Low Power Dissipation is Required
• Video Imaging
• Medical Imaging
• Radar Receivers
• IR Imaging
• Digital Communications
GENERAL DESCRIPTION
The SPT7734 is a 8-bit monolithic, low cost, ultralow power
analog-to-digital converter capable of minimum word rates
of 40 MSPS. The on-chip track-and-hold function assures
very good dynamic performance without the need for exter-
nal components. The input drive requirements are mini-
mized due to the SPT7734's low input capacitance of only
5 pF.
Power dissipation is extremely low at only 175 mW typical at
40 MSPS with a power supply of +5.0 V. The digital outputs
are +3 V or +5 V, and are user selectable. The SPT7734 has
incorporated proprietary circuit design and CMOS process-
ing technologies to achieve its advanced performance. In-
puts and outputs are TTL/CMOS compatible to interface with
TTL/CMOS logic systems. Output data format is straight
binary.
The SPT7734 is available in 28-lead SOIC and 32-lead small
(7 mm square) TQFP packages over the commercial tem-
perature range.
BLOCK DIAGRAM
ADC Section 1
A
IN
1:16
Mux
T/H
Auto-
Zero
CMP
9-Bit
SAR
9
9
D8 Overrange
D7 (MSB)
D6
P1
P2
CLK In
Timing
P15
and
Control
Enable
P16
DAC
.
.
.
ADC Section 2
.
.
.
9
.
.
.
.
.
.
ADC Section 15
ADC Section 16
T/H
Auto-
Zero
CMP
9
9-Bit
16:1
Mux/
Error
Correction
D5
D4
D3
D2
D1
DØ (LSB)
9-Bit
SAR
9
DAC
9
Data
Vali
d
Ref
In
Reference Ladder
VREF
ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)
1
25
°
C
Supply Voltages
AV
DD
......................................................................... +6 V
DV
DD
........................................................................ +6 V
Input Voltages
Analog Input .................................. -0.5 V to AV
DD
+0.5 V
V
REF ............................................................................
0 to AV
DD
CLK Input .................................................................. V
DD
AV
DD
- DV
DD ...............................................................
±100
mV
AGND - DGND ...................................................
±100
mV
Note:
Output
Digital Outputs ....................................................... 10 mA
Temperature
Operating Temperature ................................. 0 to +70
°C
Junction Temperature ......................................... +175
°C
Lead Temperature, (soldering 10 seconds) ........ +300
°C
Storage Temperature ................................ -65 to +150
°C
1. Operation at any Absolute Maximum Rating is not implied. See Electrical Specifications for proper nominal
applied conditions in typical applications.
ELECTRICAL SPECIFICATIONS
T
A
=T
MAX
to T
MAX
, AV
DD
=DV
DD
=+5.0 V, V
IN
=0 to 4 V, f
S
=40 MSPS, V
RHS
=4.0 V, V
RLS
=0.0 V, unless otherwise specified.
TEST
CONDITIONS
TEST
LEVEL
SPT7734
TYP
PARAMETERS
Resolution
DC Accuracy
Integral Nonlinearity
Differential Nonlinearity
No Missing Codes
Analog Input
Input Voltage Range
Input Resistance
Input Capacitance
Input Bandwidth
Offset
Gain Error
Reference Input
Resistance
Bandwidth
Voltage Range
V
RLS
V
RHS
V
RHS
- V
RLS
∆(V
RHF
- V
RHS
)
∆(V
RLS
- V
RLF
)
Reference Settling Time
V
RHS
V
RLS
Conversion Characteristics
Maximum Conversion Rate
Minimum Conversion Rate
Pipeline Delay (Latency)
Aperture Delay Time
Aperture Jitter Time
Dynamic Performance
Effective Number of Bits
f
IN
=3.58 MHz
f
IN
=10.3 MHz
MIN
8
MAX
UNITS
Bits
IV
IV
VI
VI
IV
V
V
V
V
VI
V
IV
IV
V
V
V
V
V
VI
IV
IV
V
V
40
2
V
RLS
50
±1.0
±0.5
Guaranteed
V
RHS
5.0
250
±2.0
±2.0
500
150
-
-
4.0
90
75
15
20
600
LSB
LSB
(Small Signal)
V
kΩ
pF
MHz
LSB
LSB
Ω
MHz
V
V
V
mV
mV
Clock Cycles
Clock Cycles
300
100
0
3.0
1.0
2.0
AV
DD
5.0
MHz
MHz
12
4.0
30
Clock Cycles
ns
ps(p-p)
VI
VI
7.3
7.2
7.8
7.7
Bits
Bits
SPT7734
2
1/27/98
ELECTRICAL SPECIFICATIONS
T
A
=T
MAX
to T
MAX
, AV
DD
=DV
DD
=+5.0 V, V
IN
=0 to 4 V, f
S
=40 MSPS, V
RHS
=4.0 V, V
RLS
=0.0 V, unless otherwise specified.
PARAMETERS
Dynamic Performance
Signal-to-Noise Ratio
(without Harmonics)
f
IN
=3.58 MHz
f
IN
=10.3 MHz
Harmonic Distortion
f
IN
=3.58 MHz
f
IN
=10.3 MHz
Signal-to-Noise and Distortion
(SINAD)
f
IN
=3.58 MHz
f
IN
=10.3 MHz
Spurious Free Dynamic Range
Differential Phase
Differential Gain
Intermodulation Distortion
Inputs
Logic 1 Voltage
Logic 0 Voltage
Maximum Input Current Low
Maximum Input Current High
Input Capacitance
Digital Outputs
Logic 1 Voltage
Logic 0 Voltage
t
RISE
t
FALL
Output Enable to Data Output Delay
Power Supply Requirements
Voltages
OV
DD
DV
DD
AV
DD
Currents
AI
DD
DI
DD
Power Dissipation
I
OH
= 0.5 mA
I
OL
= 1.6 mA
15 pF load
15 pF load
20 pF load, T
A
= +25
°C
50 pF load over temp.
TEST
CONDITIONS
TEST
LEVEL
MIN
SPT7734
TYP
MAX
UNITS
VI
VI
9 Distortion bins from
1024 pt FFT
VI
VI
46
45
53
53
49
48
57
56
dB
dB
dB
dB
VI
VI
f
IN
=1.0 MHz
V
V
V
46
45
49
48
63
±0.3
±0.3
TBD
dB
dB
dB
Degree
%
dB
V
V
µA
µA
pF
V
V
ns
ns
ns
ns
V
V
V
mA
mA
mW
VI
VI
VI
VI
V
VI
VI
V
V
V
V
IV
IV
IV
VI
VI
VI
2.0
-10
-10
+5
3.5
0.4
10
10
10
22
3.0
4.75
4.75
5.0
5.25
5.25
22
23
225
0.8
+10
+10
5.0
5.0
17
18
175
TEST LEVEL CODES
All electrical characteristics are subject to the
following conditions:
All parameters having min/max specifications
are guaranteed. The Test Level column indi-
cates the specific device testing actually per-
formed during production and Quality Assur-
ance inspection. Any blank section in the data
column indicates that the specification is not
tested at the specified condition.
TEST LEVEL
I
II
III
IV
V
VI
TEST PROCEDURE
100% production tested at the specified temperature.
100% production tested at T
A
=25
°C,
and sample
tested at the specified temperatures.
QA sample tested only at the specified temperatures.
Parameter is guaranteed (but not tested) by design
and characterization data.
Parameter is a typical value for information purposes
only.
100% production tested at T
A
= 25
°C.
Parameter is
guaranteed over specified temperature range.
SPT7734
3
1/27/98
TYPICAL INTERFACE CIRCUIT
Very few external components are required to achieve the
stated device performance. Figure 1 shows the typical inter-
face requirements when using the SPT7734 in normal circuit
operation. The following sections provide descriptions of the
major functions and outline critical performance criteria to
consider for achieving the optimal device performance.
Figure 1 - Typical Interface Circuit
Ref In
(+4 V)
VRHF
VRHS
VRLS
VRLF
VIN
VIN
VCAL
CLK IN
CLK
DAV
AVDD
AGND
DGND* DVDD
D8
The high sample rate is achieved by using multiple SAR ADC
sections in parallel, each of which samples the input signal in
sequence. Each ADC uses 16 clock cycles to complete a
conversion. The clock cycles are allocated as follows:
Table II - Clock Cycles
Clock
1
2
3
4
5-15
16
Operation
Reference zero sampling
Auto-zero comparison
Auto-calibrate comparison
Input sample
9-bit SAR conversion
Data transfer
SPT7734
D0
Interfacing
Logics
EN
The 16 phase clock, which is derived from the input clock,
synchronizes these events. The timing signals for adjacent
ADC sections are shifted by one clock cycle so that the analog
input is sampled on every cycle of the input clock by exactly
one ADC section. After 16 clock periods, the timing cycle
repeats. The latency from analog input sample to the corre-
sponding digital output is 12 clock cycles.
• Since only 16 comparators are used, a huge power savings
is realized.
• The auto-zero operation is done using a closed loop
system that uses multiple samples of the comparators
response to a reference zero.
FB1
FB2
+D5
+A5
Enable/Tri-State
(Enable = Active Low)
FB3
+A5
AGND
DGND
+D5
+
10 µF
+5 V
Analog
+5 V
Analog
RTN
*To reduce the possibility of latch-up, avoid
connecting the DGND pins of the ADC to the
digital ground of the system.
+
10 µF
+5 V
Digital
RTN
+5 V
Digital
• The auto-calibrate operation, which calibrates the gain
of the MSB reference and the LSB reference, is also
done with a closed loop system. Multiple samples of the
gain error are integrated to produce a calibration voltage for
each ADC section.
• Capacitive displacement currents, which can induce sam-
pling error, are minimized since only one comparator
samples the input during a clock cycle.
• The total input capacitance is very low since sections of the
converter which are not sampling the signal are isolated
from the input by transmission gates.
VOLTAGE REFERENCE
The SPT7734 requires the use of a single external voltage
reference for driving the high side of the reference ladder. It
must be within the range of 3 V to 5 V. The lower side of the
ladder is typically tied to AGND (0.0 V), but can be run up to
2.0 V with a second reference. The analog input voltage
range will track the total voltage difference measured be-
tween the ladder sense lines, V
RHS
and V
RLS
.
Force and sense taps are provided to ensure accurate and
stable setting of the upper and lower ladder sense line
voltages across part-to-part and temperature variations. By
using the configuration shown in figure 2, offset and gain
errors of less than
±2
LSB can be obtained.
SPT7734
5
1/27/98
NOTES: 1) FB3 is to be located as closely to the device as possible.
2) There should be no additional connections to the right of FB1 and FB2.
3) All capacitors are 0.1 µF surface-mount unless otherwise specified.
4) FB1, FB2 and FB3 are 10 µH inductors or ferrite beads.
POWER SUPPLIES AND GROUNDING
Fairchild suggests that both the digital and the analog supply
voltages on the SPT7734 be derived from a single analog
supply as shown in figure 1. A separate digital supply should
be used for all interface circuitry. Fairchild suggests using
this power supply configuration to prevent a possible latch-
up condition on power up.
OPERATING DESCRIPTION
The general architecture for the CMOS ADC is shown in the
block diagram. The design contains 16 identical successive
approximation ADC sections, all operating in parallel, a 16-
phase clock generator, an 9-bit 16:1 digital output multi-
plexer, correction logic, and a voltage reference generator
which provides common reference levels for each ADC section.
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