SPD30N06S2L-13
OptiMOS
®
Power-Transistor
Feature
•
N-Channel
Product Summary
V
DS
R
DS(on)
I
D
55
13
30
P- TO252 -3-11
V
mΩ
A
•
Enhancement mode
•
Logic Level
•
175°C operating temperature
•
Avalanche rated
•
dv/dt rated
Type
SPD30N06S2L-13
Package
Ordering Code
P- TO252 -3-11 Q67040-S4254
Marking
2N06L13
Maximum Ratings,
at
T
j
= 25 °C, unless otherwise specified
Parameter
Symbol
Continuous drain current
1)
T
C
=25°C
Value
30
30
Unit
A
I
D
Pulsed drain current
T
C
=25°C
I
D puls
E
AS
E
AR
dv/dt
V
GS
P
tot
T
j ,
T
stg
120
240
13.6
6
±20
136
-55... +175
55/175/56
kV/µs
V
W
°C
mJ
Avalanche energy, single pulse
I
D
=30 A ,
V
DD
=25V,
R
GS
=25Ω
Repetitive avalanche energy, limited by
T
jmax
2)
Reverse diode dv/dt
I
S
=30A,
V
DS
=44V,
di/dt=200A/µs,
T
jmax
=175°C
Gate source voltage
Power dissipation
T
C
=25°C
Operating and storage temperature
IEC climatic category; DIN IEC 68-1
Page 1
2003-05-09
SPD30N06S2L-13
Thermal Characteristics
Parameter
Characteristics
Thermal resistance, junction - case
Thermal resistance, junction - ambient, leaded
SMD version, device on PCB:
@ min. footprint
@ 6 cm
2
cooling area
3)
Symbol
min.
R
thJC
R
thJA
R
thJA
-
-
-
-
Values
typ.
0.69
-
-
-
max.
1.1
100
75
50
Unit
K/W
Electrical Characteristics,
at
T
j
= 25 °C, unless otherwise specified
Parameter
Static Characteristics
Drain-source breakdown voltage
V
GS
=0V,
I
D
=1mA
Symbol
min.
V
(BR)DSS
V
GS(th)
I
DSS
-
-
I
GSS
R
DS(on)
R
DS(on)
-
-
-
55
1.2
Values
typ.
-
1.6
max.
-
2
Unit
V
Gate threshold voltage,
V
GS
=
V
DS
I
D
=80µA
Zero gate voltage drain current
V
DS
=55V,
V
GS
=0V,
T
j
=25°C
V
DS
=55V,
V
GS
=0V,
T
j
=125°C
µA
0.01
1
1
12.5
9.7
1
100
100
17
13
nA
mΩ
Gate-source leakage current
V
GS
=20V,
V
DS
=0V
Drain-source on-state resistance
V
GS
=4.5V,
I
D
=30A
Drain-source on-state resistance
V
GS
=10V,
I
D
=30A
1Current limited by bondwire ; with an
R
thJC
= 1.1K/W the chip is able to carry
I
D
= 71A at 25°C, for detailed
information see app.-note ANPS071E available at
www.infineon.com/optimos
2Defined by design. Not subject to production test.
3Device on 40mm*40mm*1.5mm epoxy PCB FR4 with 6cm² (one layer, 70 µm thick) copper area for drain
connection. PCB is vertical without blown air.
Page 2
2003-05-09
SPD30N06S2L-13
Electrical Characteristics
Parameter
Dynamic Characteristics
Transconductance
Input capacitance
Output capacitance
Reverse transfer capacitance
Turn-on delay time
Rise time
Turn-off delay time
Fall time
Gate Charge Characteristics
Gate to source charge
Gate to drain charge
Gate charge total
Gate plateau voltage
Q
gs
Q
gd
Q
g
V
DD
=44V,
I
D
=30A,
V
GS
=0 to 10V
V
DD
=44V,
I
D
=30A
Symbol
Conditions
min.
Values
typ.
53
1725
404
120
7
14
8
13
max.
-
Unit
g
fs
C
iss
C
oss
C
rss
t
d(on)
t
r
t
d(off)
t
f
V
DS
≥2*I
D
*R
DS(on)max
,
I
D
=30A
V
GS
=0V,
V
DS
=25V,
f=1MHz
27
-
-
-
-
-
-
-
S
2300 pF
540
180
11
21
12
20
ns
V
DD
=30V,
V
GS
=4.5V,
I
D
=30A,
R
G
=3.6Ω
-
-
-
-
6
17
52
3.4
8
26
69
-
nC
V
(plateau)
V
DD
=44V,
I
D
=30A
V
Reverse Diode
Inverse diode continuous
forward current
Inv. diode direct current, pulsed
Inverse diode forward voltage
Reverse recovery time
Reverse recovery charge
I
SM
V
SD
t
rr
Q
rr
V
GS
=0V,
I
F
=30A
V
R
=30V,
I
F =
l
S
,
di
F
/dt=100A/µs
I
S
T
C
=25°C
-
-
-
-
-
-
-
0.9
33
71
30
120
1.3
41
90
A
V
ns
nC
Page 3
2003-05-09
SPD30N06S2L-13
5 Typ. output characteristic
I
D
=
f
(V
DS
);
T
j
=25°C
parameter:
t
p
= 80 µs
SPD30N06S2L-13
6 Typ. drain-source on resistance
R
DS(on)
=
f
(I
D
)
parameter:
V
GS
m
Ω
V
[V]
GS
a
b
75
A
P
tot
= 136W
42
SPD30N06S2L-13
c
d
e
f
i
h
36
3.0
3.2
3.4
3.6
3.8
4.0
4.5
7.0
10.0
g
60
55
50
f
c
d
e
R
DS(on)
32
28
24
20
16
g
h
i
I
D
45
40
35
30
25
20
15
10
5
0
0
0.5
1
1.5
2
2.5
3
3.5
e
f
g
h
d
i
c
12
b
8
4
0
5
0
10
20
30
40
50
V
GS
[V] =
c
3.4
d
3.6
e
3.8
f
4.0
g
4.5
h
i
7.0 10.0
a
4
V
A
65
V
DS
I
D
7 Typ. transfer characteristics
I
D
=
f
(
V
GS
);
V
DS
≥
2 x
I
D
x
R
DS(on)max
parameter:
t
p
= 80 µs
60
8 Typ. forward transconductance
g
fs
= f(I
D
);
T
j
=25°C
parameter:
g
fs
70
A
S
50
45
50
35
30
25
20
g
fs
40
30
20
10
I
D
40
15
10
5
0
0
0.5
1
1.5
2
2.5
3
3.5
4
V
5
V
GS
0
0
10
20
30
40
50
60
A
80
I
D
Page 5
2003-05-09
京公网安备 11010802033920号
EEWORLD
