PBLS2002D
20 V PNP BISS loadswitch
Rev. 02 — 27 August 2009
Product data sheet
1. Product profile
1.1 General description
PNP low V
CEsat
Breakthrough in Small Signal (BISS) transistor and NPN Resistor-
Equipped Transistor (RET) in a SOT457 (SC-74) small Surface Mounted Device (SMD)
plastic package.
1.2 Features
I
I
I
I
I
Low V
CEsat
(BISS) and resistor-equipped transistor in one package
Low threshold voltage (< 1 V) compared to MOSFET
Low drive power required
Space-saving solution
Reduction of component count
1.3 Applications
I
I
I
I
Supply line switches
Battery charger switches
High-side switches for LEDs, drivers and backlights
Portable equipment
1.4 Quick reference data
Table 1.
Symbol
V
CEO
I
C
R
CEsat
Quick reference data
Parameter
collector-emitter voltage
collector current (DC)
collector-emitter saturation
resistance
collector-emitter voltage
output current
bias resistor 1 (input)
bias resistor ratio
I
C
=
−1
A;
I
B
=
−100
mA
open base
[1]
Conditions
open base
Min
-
-
-
Typ
-
-
185
Max
−20
−1
280
Unit
V
A
mΩ
TR1; PNP low V
CEsat
transistor
TR2; NPN resistor-equipped transistor
V
CEO
I
O
R1
R2/R1
[1]
-
-
3.3
0.8
-
-
4.7
1
50
100
6.1
1.2
V
mA
kΩ
Pulse test: t
p
≤
300
µs; δ ≤
0.02
NXP Semiconductors
PBLS2002D
20 V PNP BISS loadswitch
2. Pinning information
Table 2.
Pin
1
2
3
4
5
6
Pinning
Description
emitter TR1
base TR1
output (collector) TR2
GND (emitter) TR2
input (base) TR2
collector TR1
1
2
3
sym036
Simplified outline
6
5
4
Symbol
6
5
4
1
2
3
R1
R2
TR2
TR1
3. Ordering information
Table 3.
Ordering information
Package
Name
PBLS2002D
SC-74
Description
plastic surface mounted package; 6 leads
Version
SOT457
Type number
4. Marking
Table 4.
Marking codes
Marking code
F7
Type number
PBLS2002D
5. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
V
CBO
V
CEO
V
EBO
I
C
I
CM
I
B
I
BM
P
tot
Parameter
collector-base voltage
collector-emitter voltage
emitter-base voltage
collector current (DC)
peak collector current
base current (DC)
peak base current
total power dissipation
t
p
≤
300
µs
T
amb
≤
25
°C
[1]
[2]
[3]
Conditions
open emitter
open base
open collector
t
p
≤
300
µs
Min
-
-
-
-
-
-
-
-
-
-
Max
−20
−20
−5
−1
−2
−0.3
−0.6
250
350
400
Unit
V
V
V
A
A
A
A
mW
mW
mW
TR1; PNP low V
CEsat
transistor
PBLS2002D_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 27 August 2009
2 of 16
NXP Semiconductors
PBLS2002D
20 V PNP BISS loadswitch
Table 5.
Limiting values
…continued
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
V
CBO
V
CEO
V
EBO
V
I
Parameter
collector-base voltage
collector-emitter voltage
emitter-base voltage
input voltage
positive
negative
I
O
I
CM
P
tot
P
tot
output current
peak collector current
total power dissipation
total power dissipation
t
p
≤
300
µs
T
amb
≤
25
°C
[1]
Conditions
open emitter
open base
open collector
Min
-
-
-
-
-
-
-
-
-
-
-
−65
-
−65
Max
50
50
10
+30
−10
100
100
200
400
530
600
+150
150
+150
Unit
V
V
V
V
V
mA
mA
mW
mW
mW
mW
°C
°C
°C
TR2; NPN resistor-equipped transistor
Per device
[1]
[2]
[3]
T
stg
T
j
T
amb
[1]
[2]
[3]
storage temperature
junction temperature
ambient temperature
Device mounted on an FR4 Printed-Circuit Board (PCB), single-sided copper, tin-plated and standard
footprint.
Device mounted on an FR4 PCB, single-sided copper, tin-plated, mounting pad for collector 1cm
2
.
Device mounted on a ceramic PCB, Al
2
O
3
, standard footprint.
0.8
P
tot
(W)
(1)
006aaa414
0.6
(2)
(3)
0.4
0.2
0
0
40
80
120
160
T
amb
(°C)
(1) Ceramic PCB, Al
2
O
3
, standard footprint
(2) FR4 PCB, mounting pad for collector 1cm
2
(3) FR4 PCB, standard footprint
Fig 1.
PBLS2002D_2
Power derating curves
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 27 August 2009
3 of 16
NXP Semiconductors
PBLS2002D
20 V PNP BISS loadswitch
6. Thermal characteristics
Table 6.
Symbol
Per device
R
th(j-a)
thermal resistance from
junction to ambient
in free air
[1]
[2]
[3]
Thermal characteristics
Parameter
Conditions
Min
-
-
-
Typ
-
-
-
Max
315
236
210
Unit
K/W
K/W
K/W
[1]
[2]
[3]
Device mounted on an FR4 PCB, single-sided copper, tin-plated and standard footprint.
Device mounted on an FR4 PCB, single-sided copper, tin-plated, mounting pad for collector 1cm
2
.
Device mounted on a ceramic PCB, Al
2
O
3
, standard footprint.
duty cycle =
1
Z
th(j-a)
0.75
(K/W)
0.5
0.33
10
2
0.2
0.1
0.05
10
0.02
0.01
10
3
006aaa415
1
0
10
−1
10
−5
10
−4
10
−3
10
−2
10
−1
1
10
10
2
t
p
(s)
10
3
FR4 PCB, standard footprint
Fig 2.
TR1 (PNP): Transient thermal impedance from junction to ambient as a function of pulse time; typical
values
PBLS2002D_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 27 August 2009
4 of 16
NXP Semiconductors
PBLS2002D
20 V PNP BISS loadswitch
10
3
Z
th(j-a)
(K/W)
10
2
δ
=1
0.75
0.5
0.33
0.2
0.1
0.05
10
0.02
0.01
0
1
10
−5
10
−4
10
−3
10
−2
10
−1
006aaa463
1
10
10
2
t
p
(s)
10
3
FR4 PCB, mounting pad for collector 1cm
2
Fig 3.
TR1 (PNP): Transient thermal impedance from junction to ambient as a function of pulse time; typical
values
006aaa464
10
3
Z
th(j-a)
(K/W)
δ
= 1
0.75
0.5
10
2
0.33
0.2
0.1
0.05
10
0.02
0.01
0
1
10
−5
10
−4
10
−3
10
−2
10
−1
1
10
10
2
t
p
(s)
10
3
Ceramic PCB, Al
2
O
3
, standard footprint
Fig 4.
TR1 (PNP): Transient thermal impedance from junction to ambient as a function of pulse time; typical
values
PBLS2002D_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 27 August 2009
5 of 16
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