Cyclone V Device Overview
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CV-51001 | 2018.05.07
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Contents
Contents
Cyclone V Device Overview................................................................................................. 3
Key Advantages of Cyclone V Devices............................................................................. 3
Summary of Cyclone V Features.....................................................................................4
Cyclone V Device Variants and Packages......................................................................... 5
Cyclone V E........................................................................................................5
Cyclone V GX..................................................................................................... 7
Cyclone V GT......................................................................................................9
Cyclone V SE.................................................................................................... 12
Cyclone V SX.................................................................................................... 14
Cyclone V ST.................................................................................................... 15
I/O Vertical Migration for Cyclone V Devices................................................................... 18
Adaptive Logic Module................................................................................................ 18
Variable-Precision DSP Block........................................................................................19
Embedded Memory Blocks........................................................................................... 21
Types of Embedded Memory............................................................................... 21
Embedded Memory Capacity in Cyclone V Devices................................................. 21
Embedded Memory Configurations.......................................................................22
Clock Networks and PLL Clock Sources.......................................................................... 22
FPGA General Purpose I/O........................................................................................... 23
PCIe Gen1 and Gen2 Hard IP....................................................................................... 24
External Memory Interface.......................................................................................... 24
Hard and Soft Memory Controllers....................................................................... 24
External Memory Performance............................................................................ 25
HPS External Memory Performance...................................................................... 25
Low-Power Serial Transceivers......................................................................................25
Transceiver Channels......................................................................................... 25
PMA Features................................................................................................... 26
PCS Features.................................................................................................... 27
SoC with HPS.............................................................................................................28
HPS Features....................................................................................................28
FPGA Configuration and Processor Booting............................................................30
Hardware and Software Development.................................................................. 31
Dynamic and Partial Reconfiguration............................................................................. 31
Dynamic Reconfiguration....................................................................................31
Partial Reconfiguration....................................................................................... 31
Enhanced Configuration and Configuration via Protocol.................................................... 32
Power Management.................................................................................................... 33
Document Revision History for Cyclone V Device Overview...............................................33
Cyclone V Device Overview
2
CV-51001 | 2018.05.07
Cyclone V Device Overview
The Cyclone
®
V devices are designed to simultaneously accommodate the shrinking
power consumption, cost, and time-to-market requirements; and the increasing
bandwidth requirements for high-volume and cost-sensitive applications.
Enhanced with integrated transceivers and hard memory controllers, the Cyclone V
devices are suitable for applications in the industrial, wireless and wireline, military,
and automotive markets.
Related Information
Cyclone V Device Handbook: Known Issues
Lists the planned updates to the Cyclone V Device Handbook chapters.
Key Advantages of Cyclone V Devices
Table 1.
Key Advantages of the Cyclone V Device Family
Advantage
Lower power consumption
•
•
Improved logic integration and
differentiation capabilities
•
•
•
•
•
•
•
•
•
•
Supporting Feature
Built on TSMC's 28 nm low-power (28LP) process technology and includes an
abundance of hard intellectual property (IP) blocks
Up to 40% lower power consumption than the previous generation device
8-input adaptive logic module (ALM)
Up to 13.59 megabits (Mb) of embedded memory
Variable-precision digital signal processing (DSP) blocks
3.125 gigabits per second (Gbps) and 6.144 Gbps transceivers
Hard memory controllers
Tight integration of a dual-core Arm Cortex-A9 MPCore processor, hard IP, and an
FPGA in a single Cyclone V system-on-a-chip (SoC)
Supports over 128 Gbps peak bandwidth with integrated data coherency between
the processor and the FPGA fabric
Requires only two core voltages to operate
Available in low-cost wirebond packaging
Includes innovative features such as Configuration via Protocol (CvP) and partial
reconfiguration
Increased bandwidth capacity
Hard processor system (HPS)
with integrated Arm* Cortex*-A9
MPCore* processor
Lowest system cost
Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus
and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other
countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in
accordance with Intel's standard warranty, but reserves the right to make changes to any products and services
at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any
information, product, or service described herein except as expressly agreed to in writing by Intel. Intel
customers are advised to obtain the latest version of device specifications before relying on any published
information and before placing orders for products or services.
*Other names and brands may be claimed as the property of others.
ISO
9001:2008
Registered
Cyclone V Device Overview
CV-51001 | 2018.05.07
Summary of Cyclone V Features
Table 2.
Summary of Features for Cyclone V Devices
Feature
Technology
•
•
•
•
•
High-performance
FPGA fabric
Internal memory
blocks
Description
TSMC's 28-nm low-power (28LP) process technology
1.1 V core voltage
Wirebond low-halogen packages
Multiple device densities with compatible package footprints for seamless migration between
different device densities
RoHS-compliant and leaded
(1)
options
Packaging
Enhanced 8-input ALM with four registers
•
•
M10K—10-kilobits (Kb) memory blocks with soft error correction code (ECC)
Memory logic array block (MLAB)—640-bit distributed LUTRAM where you can use up to 25%
of the ALMs as MLAB memory
•
Native support for up to three signal processing precision levels
(three 9 x 9, two 18 x 18, or one 27 x 27 multiplier) in the same
variable-precision DSP block
64-bit accumulator and cascade
Embedded internal coefficient memory
Preadder/subtractor for improved efficiency
Embedded Hard IP
blocks
Variable-precision DSP
•
•
•
Memory controller
Embedded transceiver
I/O
Clock networks
•
•
•
•
•
•
•
•
•
•
•
•
•
•
DDR3, DDR2, and LPDDR2 with 16 and 32 bit ECC support
PCI Express* (PCIe*) Gen2 and Gen1 (x1, x2, or x4) hard IP with
multifunction support, endpoint, and root port
Up to 550 MHz global clock network
Global, quadrant, and peripheral clock networks
Clock networks that are not used can be powered down to reduce dynamic power
Precision clock synthesis, clock delay compensation, and zero delay buffering (ZDB)
Integer mode and fractional mode
875 megabits per second (Mbps) LVDS receiver and 840 Mbps LVDS transmitter
400 MHz/800 Mbps external memory interface
On-chip termination (OCT)
3.3 V support with up to 16 mA drive strength
614 Mbps to 6.144 Gbps integrated transceiver speed
Transmit pre-emphasis and receiver equalization
Dynamic partial reconfiguration of individual channels
Single or dual-core Arm Cortex-A9 MPCore processor-up to 925 MHz maximum frequency with
support for symmetric and asymmetric multiprocessing
Interface peripherals—10/100/1000 Ethernet media access control (EMAC), USB 2.0
On-The-GO (OTG) controller, quad serial peripheral interface (QSPI) flash controller, NAND
flash controller, Secure Digital/MultiMediaCard (SD/MMC) controller, UART, controller area
network (CAN), serial peripheral interface (SPI), I
2
C interface, and up to 85 HPS GPIO
interfaces
System peripherals—general-purpose timers, watchdog timers, direct memory access (DMA)
controller, FPGA configuration manager, and clock and reset managers
On-chip RAM and boot ROM
continued...
Phase-locked loops
(PLLs)
FPGA General-purpose
I/Os (GPIOs)
Low-power high-speed
serial interface
HPS
(Cyclone V SE, SX,
and ST devices only)
•
•
(1)
Contact Intel for availability.
Cyclone V Device Overview
4
Cyclone V Device Overview
CV-51001 | 2018.05.07
Feature
•
•
•
Configuration
•
•
•
•
•
•
•
Description
HPS–FPGA bridges—include the FPGA-to-HPS, HPS-to-FPGA, and lightweight HPS-to-FPGA
bridges that allow the FPGA fabric to issue transactions to slaves in the HPS, and vice versa
FPGA-to-HPS SDRAM controller subsystem—provides a configurable interface to the multiport
front end (MPFE) of the HPS SDRAM controller
Arm CoreSight
™
JTAG debug access port, trace port, and on-chip trace storage
Tamper protection—comprehensive design protection to protect your valuable IP investments
Enhanced advanced encryption standard (AES) design security features
CvP
Dynamic reconfiguration of the FPGA
Active serial (AS) x1 and x4, passive serial (PS), JTAG, and fast passive parallel (FPP) x8 and
x16 configuration options
Internal scrubbing
(2)
Partial reconfiguration
(3)
Cyclone V Device Variants and Packages
Table 3.
Device Variants for the Cyclone V Device Family
Variant
Cyclone V E
Cyclone V GX
Cyclone V GT
Cyclone V SE
Cyclone V SX
Cyclone V ST
Description
Optimized for the lowest system cost and power requirement for a wide spectrum of general logic
and DSP applications
Optimized for the lowest cost and power requirement for 614 Mbps to 3.125 Gbps transceiver
applications
The FPGA industry’s lowest cost and lowest power requirement for 6.144 Gbps transceiver
applications
SoC with integrated Arm-based HPS
SoC with integrated Arm-based HPS and 3.125 Gbps transceivers
SoC with integrated Arm-based HPS and 6.144 Gbps transceivers
Cyclone V E
This section provides the available options, maximum resource counts, and package
plan for the Cyclone V E devices.
The information in this section is correct at the time of publication. For the latest
information and to get more details, refer to the Product Selector Guide.
Related Information
Product Selector Guide
Provides the latest information about Intel products.
(2)
The SEU internal scrubbing feature is available for Cyclone V E, GX, SE, and SX devices with
the "SC" suffix in the part number. For device availability and ordering, contact your local Intel
sales representatives.
The partial reconfiguration feature is available for Cyclone V E, GX, SE, and SX devices with
the "SC" suffix in the part number. For device availability and ordering, contact your local
Intel
®
sales representatives.
(3)
Cyclone V Device Overview
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