Changes to Shutdown Section ...................................................... 11
Changes to Table 8 and Table 9 .................................................... 13
Changes to Table 10 and Table 11 ................................................ 14
Changes to Ordering Guide .......................................................... 24
4/2009—Revision 0: Initial Version
Rev. C | Page 2 of 24
Data Sheet
SPECIFICATIONS
T
A
= −55°C to +150°C, V
DD
= 2.7 V to 5.5 V, unless otherwise noted.
Table 1.
Parameter
TEMPERATURE SENSOR AND ADC
Accuracy
1
Min
Typ
−0.05
Max
±0.4
2
±0.44
±0.5
±0.5
±0.7
±0.8
±1.0
Unit
°C
°C
°C
°C
°C
°C
°C
Bits
Bits
Test Conditions/Comments
ADT7410
ADC Resolution
13
16
T
A
= −40°C to +105°C, V
DD
= 3.0 V
T
A
= −40°C to +105°C, V
DD
= 2.7 V to 3.3 V
T
A
= −55°C to +125°C, V
DD
= 3.0 V
T
A
= −40°C to +105°C, V
DD
= 2.7 V to 3.6 V
T
A
= −55°C to +150°C, V
DD
= 2.7 V to 3.6 V
T
A
= −40°C to +105°C, V
DD
= 4.5 V to 5.5 V
T
A
= −55°C to +150°C, V
DD
= 2.7 V to 5.5 V
Twos complement temperature value of the sign bit
plus 12 ADC bits (power-up default resolution)
Twos complement temperature value of the sign bit
plus 15 ADC bits (Bit 7 = 1 in the configuration register)
13-bit resolution (sign + 12-bit)
16-bit resolution (sign + 15-bit)
Continuous conversion and one-shot conversion modes
First conversion on power-up only
Conversion time for 1 SPS mode
Temperature cycle = 25°C to 125°C and back to 25°C
T
A
= 25°C
T
A
= 25°C
CT and INT pins pulled up to 5.5 V
V
OH
= 5.5 V
I
OL
= 2 mA at 5.5 V, I
OL
= 1 mA at 3.3 V
Temperature Resolution
13-Bit
16-Bit
Temperature Conversion Time
Fast Temperature Conversion Time
1 SPS Conversion Time
Temperature Hysteresis
Repeatability
3
DC PSRR
DIGITAL OUTPUTS (OPEN DRAIN)
High Output Leakage Current, I
OH
Output High Current
Output Low Voltage, V
OL
Output High Voltage, V
OH
Output Capacitance, C
OUT
DIGITAL INPUTS
Input Current
Input Low Voltage, V
IL
Input High Voltage, V
IH
SCL, SDA Glitch Rejection
Pin Capacitance
POWER REQUIREMENTS
Supply Voltage
Supply Current
At 3.3 V
At 5.5 V
1 SPS Current
At 3.3 V
At 5.5 V
Shutdown Current
At 3.3 V
At 5.5 V
Power Dissipation Normal Mode
Power Dissipation 1 SPS
1
2
0.0625
0.0078
240
6
60
±0.002
±0.015
0.1
0.1
5
1
0.4
°C
°C
ms
ms
ms
°C
°C
°C/V
µA
mA
V
V
pF
µA
V
V
ns
pF
V
µA
µA
µA
µA
15
25
µA
µA
µW
µW
0.7 × V
DD
3
±1
0.4
0.7 × V
DD
50
5
2.7
210
250
46
65
2.0
5.2
700
150
10
5.5
250
300
V
IN
= 0 V to V
DD
Input filtering suppresses noise spikes of less than 50 ns
Peak current while converting, I
2
C interface inactive
Peak current while converting, I
2
C interface inactive
V
DD
= 3.3 V, 1 SPS mode, T
A
= 25°C
V
DD
= 5.5 V, 1 SPS mode, T
A
= 25°C
Supply current in shutdown mode
Supply current in shutdown mode
V
DD
= 3.3 V, normal mode at 25°C
Power dissipated for V
DD
= 3.3 V, T
A
= 25°C
Accuracy includes lifetime drift.
The equivalent 3 σ limits are ±0.33°C. This 3 σ specification is provided to enable comparison with other vendors who use these limits.
3
Based on a floating average of 10 readings.
Rev. C | Page 3 of 24
ADT7410
I
2
C TIMING SPECIFICATIONS
Data Sheet
T
A
= −55°C to +150°C, V
DD
= 2.7 V to 5.5 V, unless otherwise noted. All input signals are specified with rise time (t
R
) = fall time (t
F
) = 5 ns
(10% to 90% of V
DD
) and timed from a voltage level of 1.6 V.
Table 2.
Parameter
SERIAL INTERFACE
1, 2
SCL Frequency
SCL High Pulse Width, t
HIGH
SCL Low Pulse Width, t
LOW
SCL, SDA Rise Time, t
R
SCL, SDA Fall Time, t
F
Hold Time (Start Condition), t
HD;STA
Setup Time (Start Condition), t
SU;STA
Data Setup Time, t
SU;DAT
Setup Time (Stop Condition), t
SU;STO
Data Hold Time, t
HD;DAT
(Master)
Bus-Free Time (Between Stop and Start Condition), t
BUF
1
2
Min
0
0.6
1.3
Typ
Max
400
Unit
kHz
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
Test Conditions/Comments
See Figure 2
0.3
0.3
0.6
0.6
0.25
0.35
0.6
0
1.3
After this period, the first clock is generated
Relevant for repeated start condition
V
DD
≥ 3.0 V
V
DD
< 3.0 V
Sample tested during initial release to ensure compliance.
All input signals are specified with input rise/fall times = 3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and outputs.
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