ATF1502AS and ATF1502ASL
High-performance EEPROM
Complex Programmable Logic Device
DATASHEET
Features
High-density, High-performance, Electrically-erasable Complex Programmable
Logic Device
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32 Macrocells
5 Product Terms per Macrocell, Expandable up to 40 per Macrocell
44 Pins
7.5ns Maximum Pin-to-pin Delay
Registered Operation up to 125MHz
Enhanced Routing Resources
In-System Programmability (ISP) via JTAG
Flexible Logic Macrocell
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D/T Latch Configurable Flip-flops
Global and Individual Register Control Signals
Global and Individual Output Enable
Programmable Output Slew Rate
Programmable Output Open Collector Option
Maximum Logic Utilization by Burying a Register with a COM Output
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Automatic 10μA Standby for “L” Version
Pin-controlled 1mA Standby Mode
Programmable Pin-keeper Inputs and I/Os
Reduced-power Feature per Macrocell
Advanced Power Management Features
Available in Commercial and Industrial Temperature Ranges
Available in 44-lead PLCC and 44-lead TQFP
Advanced EEPROM Technology
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100% Tested
Completely Reprogrammable
10,000 Program/Erase Cycles
20 Year Data Retention
2000V ESD Protection
200mA Latch-up Immunity
JTAG Boundary-scan Testing to IEEE Std. 1149.1-1990 and 1149.1a-1993
Supported
PCI-compliant
Security Fuse Feature
Green (Pb/Halide-fee/RoHS Compliant) Package Options
Atmel-0995L-CPLD-ATF1502AS(L)-Datasheet_032014
Enhanced Features
Improved Connectivity (Additional Feedback Routing, Alternate Input Routing)
Output Enable Product Terms
D Latch Mode
Combinatorial Output with Registered Feedback within Any Macrocell
Three Global Clock Pins
ITD (Input Transition Detection) Circuits on Global Clocks, Inputs and I/O (“L” Versions)
Fast Registered Input from Product Term
Programmable “Pin-keeper” Option
V
CC
Power-up Reset Option
Pull-up Option on JTAG Pins TMS and TDI
Advanced Power Management Features
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Input Transition Detection
Power-down (“L” Versions)
Individual Macrocell Power Option
Disable ITD on Global Clocks, Inputs, and I/O
Description
The Atmel
®
ATF1502AS(L) is a high-performance, high-density Complex Programmable Logic Device (CPLD)
which utilizes the Atmel proven electrically-erasable technology. With 32 logic macrocells and up to 36 inputs, it
easily integrates logic from several TTL, SSI, MSI, LSI, and classic PLDs. The ATF1502AS(L)’s enhanced
routing switch matrices increase usable gate count and the odds of successful pin-locked design modifications.
The ATF1502AS(L) has up to 32 bi-directional I/O pins and four dedicated input pins, depending on the type of
device package selected. Each dedicated pin can serve as a global control signal, register clock, register reset,
or output enable. Each of these control signals can be selected for use individually within each macrocell.
Each of the 32 macrocells generates a buried feedback which goes to the global bus. Each input and I/O pin
also feeds into the global bus. The switch matrix in each logic block then selects 40 individual signals from the
global bus. Each macrocell also generates a foldback logic term that goes to a regional bus. Cascade logic
between macrocells in the ATF1502AS(L) allows fast, efficient generation of complex logic functions. The
ATF1502AS(L) contains four such logic chains, each capable of creating sum term logic with a fan-in of up to
40 product terms.
The ATF1502AS(L) macrocell, shown in
Figure 1,
is flexible enough to support highly complex logic functions
operating at high speed. The macrocell consists of five sections:
Product Terms and Product Term Select Multiplexer
OR/XOR/CASCADE Logic
Flip-flop
Output Select and Enable
Logic Array Inputs
2
ATF1502AS(L) [DATASHEET]
Atmel-0995L-CPLD-ATF1502AS(L)-Datasheet_032014
Figure 1.
ATF1502AS(L) Macrocell
SWITCH REGIONAL
MATRIX FOLDBACK
OUTPUTS
BUS
LOGIC
FOLDBACK
CASIN
GOE[0:5]
SWITCH
MATRIX
MOE
PTMUX
I/O Pin
GCK[0:2]
SLEW
RATE
I/O Pin
GCLEAR-
OPEN COLLECTOR
OPTION
CASOUT
GLOBAL BUS
MACROCELL REDUCED POWER BIT
ATF1502AS(L) [DATASHEET]
Atmel-0995L-CPLD-ATF1502AS(L)-Datasheet_032014
3
1.
Pin Configurations and Pinouts
Figure 1-1.
Pinouts
44-lead TQFP
(Top View)
I/O
I/O
I/O
VCC
GCLK2/OE2/I
GCLR/I
I/OE1
GCLK1/I
GND
GCLK3/I/O
I/O
44-lead PLCC
(Top View)
I/O
I/O
I/O
VCC
GCLK2/OE2/I
GCLR/I
OE1/I
GCLK1/I
GND
GCLK3/I/O
I/O
12
13
14
15
16
17
18
19
20
21
22
I/O
I/O
I/O
I/O
GND
VCC
I/O
PD2/I/O
I/O
I/O
I/O
44-lead TQFP
Top View
44-lead PLCC
Top View
4
ATF1502AS(L) [DATASHEET]
Atmel-0995L-CPLD-ATF1502AS(L)-Datasheet_032014
I/O
I/O
I/O
I/O
GND
VCC
I/O
PD2/I/O
I/O
I/O
I/O
18
19
20
21
22
23
24
25
26
27
28
I/O/TDI
I/O
I/O
GND
PD1/I/O
I/O
TMS/I/O
I/O
VCC
I/O
I/O
1
2
3
4
5
6
7
8
9
10
11
33
32
31
30
29
28
27
26
25
24
23
I/O
I/O/TDO
I/O
I/O
VCC
I/O
I/O
I/O/TCK
I/O
GND
I/O
TDI/I/O
I/O
I/O
GND
PD1/I/O
I/O
I/O/TMS
I/O
VCC
I/O
I/O
7
8
9
10
11
12
13
14
15
16
17
6
5
4
3
2
1
44
43
42
41
40
44
43
42
41
40
39
38
37
36
35
34
39
38
37
36
35
34
33
32
31
30
29
I/O
I/O/TDO
I/O
I/O
VCC
I/O
I/O
I/O/TCK
I/O
GND
I/O
2.
Block Diagram
Figure 2-1.
Block Diagram
Logic Block A
Regional
Foldbacks
Switch
Matrix
Macrocells
1 to 16
I/O Pins
GLOBAL
BUS
(INPUTS and FEEDBACKS BUS)
Logic Block B
I/O Pins
GOE[0:5]
GCK[0:2]
GCLEAR
GCK[0:2]
GOE[0:5]
Output
Enable
Switch
Matrix
I/O (MC32)/GCLK3
Global
Clock
Mux
GCK[0:2]
OE1/INPUT
INPUT/GCLK1
INPUT/OE2/GCLK2
Global
Clear
Mux
GCLEAR
INPUT/GCLR
Unused product terms are automatically disabled by the compiler to decrease power consumption. A security
fuse, when programmed, protects the contents of the ATF1502AS(L). Two bytes (16 bits) of User Signature are
accessible to the user for purposes such as storing project name, part number, revision, or date. The User
Signature is accessible regardless of the state of the security fuse.
The ATF1502AS(L) device is an In-System Programmable (ISP) device. It uses the industry standard 4-pin
JTAG interface (IEEE Std. 1149.1), and is fully compliant with JTAG’s Boundary-scan Description Language
(BSDL). ISP allows the device to be programmed without removing it from the printed circuit board. In addition
to simplifying the manufacturing flow, ISP also allows design modifications to be made in the field via software.
ATF1502AS(L) [DATASHEET]
Atmel-0995L-CPLD-ATF1502AS(L)-Datasheet_032014
GOE[0:5]
GCLEAR
5
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