EZ-PD™ CCG5
USB Type-C Port Controller
EZ-PD™ CCG5, USB Type-C Port Controller
General Description
EZ-PD™ CCG5 is a dual USB Type-C controller that complies with the latest USB Type-C and PD standards. EZ-PD CCG5 provides
a complete dual USB Type-C and USB-Power Delivery port control solution for PCs, notebook, and dock. It can also be used in dual
role and downstream-facing port applications. EZ-PD CCG5 uses Cypress’ proprietary M0WS8 technology with a 32-bit, 48-MHz
Arm
®
Cortex
®
-M0 processor with 128-KB flash and integrates two complete Type-C Transceivers including the Type-C termination
resistors, R
P
and R
D
. CCG5 also integrates high-voltage regulator. CCG5 is available in 40-QFN (1 port
[3]
) and 96-BGA (2 ports)
packages.
Applications
PCs, Notebook, and Dock
■
Thunderbolt hosts and devices
■
32-bit MCU Subsystem
■
■
■
48-MHz Arm Cortex-M0 CPU
128-KB Flash
12-KB SRAM
Up to two integrated timers and counters to meet response
times required by the USB-PD protocol
Four run-time serial communication blocks (SCBs) with
reconfigurable I
2
C, SPI, or UART functionality
Integrated oscillator eliminating the need for an external clock
2.75 V to 21.5 V operation
± 8-kV Contact Discharge and ±15-kV Air Gap Discharge based
on IEC61000-4-2 level 4C
Features
Type-C and USB-PD Support
Integrated USB Power Delivery (USB-PD) 3.0 support
■
Two integrated USB-PD Type-C ports
[1]
[2]
■
Integrated UFP (R
D
) and current sources for DFP (R
P
) on
both Type-C ports
■
Integrated dead battery termination for DRP (Power
Source/Sink) applications
■
Integrated VCONN FETs to power EMCA cables
■
Integrated fast role swap and extended data messaging
■
Integrated high-voltage LDO, operational up to 21.5 V
■
Integrated 2x USB Analog Mux
■
Integrated 2x SBU Analog Mux
■
Integrated 2x USB Charger detect blocks – BC v1.2, Apple
Charging (source only)
■
Integrated overvoltage protection (OVP) and overcurrent
protection (OCP) on the VBUS
■
Integrated OCP protection on the VCONN
■
Integrated high-voltage protection on CC and SBU pins to
protect against accidental shorts to the VBUS pin on the Type-C
connector
■
Integrated current sense amplifier that supports high-side
current sensing
■
Integrated gate drivers for external VBUS PFET control on
Type-C Ports
■
Supports high-voltage tolerant PFET-controlled GPIOs
■
Integrated Digital Blocks
■
■
Clocks and Oscillators
■
Low-Power Operation
■
System-Level ESD on CC, D±, and SBU Pins
■
Hot-Swappable I/Os
■
Port 1 I
2
C pins and CC1, CC2 pins are hot-swappable
6.0 mm
6.0 mm, 0.6 mm, 40-pin QFN
6.0 mm
6.0 mm, 1.0 mm, 96-ball BGA
Supports industrial temperature range (–40 °C to +85 °C)
Packages
■
■
Notes
1. UFP refers to Power Sink.
2. DFP refers to Power Source.
3. NRND (Not Recommended for New Designs). Refer to the
CCG5C Datasheet
for pin to pin compatible replacement part.
Cypress Semiconductor Corporation
Document Number: 002-17682 Rev. *M
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised March 28, 2019
EZ-PD™ CCG5
Logic Block Diagram
CCG5: Single- Chip Type C Controller
-
-
MCU Subsystem
Integrated Digital Blocks
2x TCPWM
Advanced High- Performance Bus
(AHB)
SCB
(I
2
C, SPI, UART)
(I
2
C,
SCB
SPI, UART)
I/O Subsystem
Programmable I/O Matrix
CC
VCONN
28 GPIO
Pins
ARM
CORTEX -M0
48 MHz
Flash
(128KB)
SCB
(I
2
C, SPI, UART)
SCB
(I
2
C, SPI, UART)
USB PD Subsystem x2
Baseband MAC
SRAM
(12KB )
VBUS OVP
Protection
HV Protection
On CC & SBU
Under Voltage
Protection
2x V
CONN
FETs
2x Gate Drivers
High- Side Current
sense Amplifier
System
Resources
2x SBU Analog
Mux Switch
2x2 USB Analog
Mux Switch
2x USB Charge
Detect
Baseband PHY
Hi- Voltage LDO
( 21.5V)
1x 8- bit SAR ADC
VBUS/VCONN OCP
Protection
Document Number: 002-17682 Rev. *M
Page 2 of 43
EZ-PD™ CCG5
Contents
Functional Overview ........................................................ 4
USB-PD Subsystem (SS) ............................................ 4
CPU and Memory Subsystem ..................................... 6
Power System Overview .................................................. 7
Peripherals .................................................................. 8
GPIO ........................................................................... 8
Pinouts .............................................................................. 9
Application Diagrams ..................................................... 16
Electrical Specifications ................................................ 21
Absolute Maximum Ratings ....................................... 21
Device-Level Specifications ...................................... 22
Digital Peripherals ..................................................... 25
System Resources .................................................... 26
Ordering Information ...................................................... 34
Ordering Code Definitions ......................................... 34
Packaging ........................................................................ 35
Acronyms ........................................................................ 37
Document Conventions ................................................. 38
Units of Measure ....................................................... 38
References and Links To Applications Collaterals .... 39
Document History Page ................................................. 40
Sales, Solutions, and Legal Information ...................... 43
Worldwide Sales and Design Support ....................... 43
Products .................................................................... 43
PSoC® Solutions ...................................................... 43
Cypress Developer Community ................................. 43
Technical Support ..................................................... 43
Document Number: 002-17682 Rev. *M
Page 3 of 43
EZ-PD™ CCG5
Functional Overview
USB-PD Subsystem (SS)
USB-PD Physical Layer
The CCG5 has two USB-PD subsystems consisting of the
USB-PD physical layer (PHY) block and supporting circuits. The
USB-PD PHY consists of a transmitter and receiver that commu-
nicate BMC and 4b/5b encoded data over the CC channel based
on the PD 3.0 standard. All communication is half-duplex. The
PHY practices collision avoidance to minimize communication
errors on the channel.
In addition, the CCG5 USB-PD block includes all termination
resistors (R
P
and R
D
) and their switches as required by the USB
Type-C spec. R
P
and R
D
resistors are required to implement
connection detection, plug orientation detection, and for estab-
lishing the USB source/sink roles.
The integrated R
P
resistor enables CCG5 to be configured as a
DFP. The R
P
resistor is implemented as a current source and can
be programmed to support the complete range of current
capacity on the VBUS defined in the USB Type-C Spec.
The R
D
resistor is used to identify CCG5 as a UFP in a DRP
application. The R
D
resistor on CC pins is required even when
the part is not powered for dead battery termination detection
and charging.
Figure 1. USB-PD Subsystem
To/From System Resources
vref
iref
To/ from AHB
8-bit ADC
To support the latest USB-PD 3.0 specification, CCG5 has imple-
mented the Fast Role Swap (FRS) feature. The FRS feature
enables externally powered docks and hubs to rapidly switch to
bus power when their external power supply is removed. CCG5
also supports DeepSleep in notebook systems where CCG5 is
expecting FRS detection.
For more details, refer to Section 6.3.17 in the
USB-PD 3.0
specification.
CCG5 is designed to be fully interoperable with revision 3.0 of
the USB Power Delivery specification as well as revision 2.0 of
the USB Power Delivery specification.
CCG5 supports Extended Messages containing data of up to 260
bytes. The Extended Messages will be larger than expected by
the USB-PD 2.0 hardware. To accommodate Revision 2.0 based
systems, a Chunking mechanism is implemented such that
messages are limited to Revision 2.0 sizes unless it is
discovered that both systems support longer message lengths.
From AMUX
VCONN FET Enable
TxRx Enable
Digital Baseband PHY
Tx_data
from AHB
Enable Logic
Tx
SRAM
CRC
4b5b
Encoder
SOP
Insert
BMC
Encoder
TX
RX
Rp
V5V
VCONN
FETs
CC1
RD1
CC2
Rx_data
to AHB
Rx
SRAM
4b5b
Decoder
SOP
Detect
BMC
Decoder
Comp
Ref
Active
Rd
DB
Rd
CC control
CC detect
Deep Sleep Reference Enable
Functional, Wakeup Interrupts
Deep Sleep Vref &
Iref Gen (common
for both ports)
RD2
8kV IEC ESD
Analog Baseband PHY
vref, iref
RD1 shorted to CC1 and RD2 shorted to CC2 for DRP applications using
bondwire. For DFP applications, RD1 and RD2 not shorted to CC1 and CC2.
Dead Battery (DB) Rd termination removed after MCU boots up
Document Number: 002-17682 Rev. *M
Page 4 of 43
EZ-PD™ CCG5
VCONN FET
CCG5 has two power supply inputs, V5V_P1 and V5V_P2 pins,
for providing power to EMCA cables through integrated VCONN
FETs. There are two VCONN FETs for each PD port to power
either CC1 or CC2 pins. These FETs can provide 1.5-W power
over VCONN on the CC1 and CC2 pins for the EMCA cables.
CCG5 also supports integrated OCP on VCONN.
ADC
The USB-PD subsystem contains one 8-bit successive approxi-
mation register (SAR) for analog-to-digital conversions (ADC).
The ADCs include an 8-bit DAC and a comparator. The DAC
output forms the positive input of the comparator. The negative
input of the comparator is from a 4-input multiplexer. The four
inputs of the multiplexer are a pair of global analog multiplex
busses, an internal bandgap voltage, and an internal voltage
proportional to the absolute temperature. All GPIOs on the chip
have access to the ADCs through the chip-wide analog mux bus.
The CC1 and CC2 pins of both Type-C ports are not available to
connect to the mux bus.
SBU Mux
The SBU switch mux contains 2x1 Mux and a single 2x2 cross
bar SBU switch per the Type-C port. The 2x1 MUX enables you
to select between the Display Port or Thunderbolt alternate
mode and the single-ended 2x2 switch enables you to route
signals to the appropriate SBU1/2 based on CC (Type-C plug)
orientation.
The AUX port of the SBU switch supports only differential
signals. Non-differential signals on the AUX port cause signal
coupling at the output of the SBU switch. The LS port of the SBU
switch supports both non-differential and differential signals.
Figure 2. CCG5 SBU Crossbar Switch Block Diagram
USB HS Mux
The HS Mux contains a 2×2 cross bar switch to route the system
D± lines to the Type-C top or bottom ports based on the CC
(Type-C plug) orientation. The unused D± top or bottom lines can
be connected to a UART (Debug) port. The maximum operating
frequency of UART must be 1 Mbps.
The HS Mux also contains charger detection/emulation for
detecting USB BC 1.2 (source only) and Apple terminations. The
charger detection block is connected to the D± from the system
as shown in
Figure 3.
To meet the HS eye diagram requirements with sufficient margin,
follow these guidelines:
■
It is recommended to keep the total USB HS signal trace
lengths (USB 2.0 host to CCG5 + CCG5 to Type-C connector
pins) to 4 inches.
Total USB HS signal trace lengths can be increased up to 8
inches by adjusting the drive strength on the USB 2.0 host.
The differential impedance across the DP/DM signal traces
shall be 90 Ω.
Trace width shall be 6 mils.
Air Gap (distance between lines) shall be 8 mils.
■
■
■
■
Figure 3. CCG5 DP/DM Switch Block Diagram
Overvoltage and Undervoltage Protection on VBUS
CCG5 implements an undervoltage/overvoltage (UV/OV)
detection circuit for the VBUS supply. The threshold for OV and
UV detection can be set independently. Both UV and OV detector
have programmable thresholds and is controlled by the
firmware.
Overcurrent Protection on VBUS
CCG5 integrates a high-side current sense amplifier to detect
overcurrent on the VBUS. Overcurrent protection is enabled by
sensing the current through the 10-m sense resistor connected
between the “CSP_Px” and “CSN_Px” pins.
Document Number: 002-17682 Rev. *M
Page 5 of 43
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