The DRF1300 is a push-pull hybrid containing two high power gate
drivers and two power MOSFETs. It was designed to provide the sys-
tem designer increased
fl
exibility, higher performance, and lowered cost
over a non-integrated solution. This low parasitic approach, coupled
IN
with the Schmitt trigger input, Kelvin signal ground, Anti-Ring function
Invert and Non-invert select pin provide improved stability and control in
Kilowatt to Multi-Kilowatt, High Frequency ISM applications.
D
S
D
DRIVER 30A
MOSFETS
S
FEATURES
• Switching Frequency: DC TO 30MHz
• Inverting Non-Inverting Select
• Low Pulse Width Distortion
• Single Power Supply (Per Section)
• 1V CMOS Schmitt Trigger Input 1V
Hysteresis
• Switching Speed 3-4ns
• B
Vds
= 500V
• I
ds
= 30A max. Per-section
• R
ds(on)
≤
.24 Ohm
• P
D
= 550W Per-section
• RoHS Compliant
TYPICAL APPLICATIONS
• Class C, D and E RF Generators
• Switch Mode Power Amplifiers
• HV Pulse Generators
• Ultrasound Transducer Drivers
• Acoustic Optical Modulators
Driver Absolute Maximum Ratings
Symbol
V
DD
IN, FN
I
O PK
T
JMAX
Parameter
Supply Voltage
Input Single Voltages
Output Current Peak
Operating Temperature
Ratings
15
-.7 to +5.5
8
175
Unit
V
A
°C
Driver Specifications
Symbol
V
DD
IN
IN
(R)
IN
(F)
I
DDQ
I
O
C
iss
R
IN
V
T(ON)
V
T(OFF)
T
DLY
t
r
t
f
Parameter
Supply Voltage
Input Voltage
Input Voltage Rising Edge
Input Voltage Falling Edge
Quiescent Current
Output Current
Input Capacitance
Input Parallel Resistance
Input, Low to High Out (See Truth Table)
Input, High to Low Out (See Truth Table)
Time Delay (throughput)
Rise Time
Fall Time
0.8
1.9
38
5
5
Min
10
3
5
3
3
2
8
3
1
1.1
2.2
MΩ
V
ns
ns
050-4971 Rev E 12-2009
Typ
Max
15
Unit
V
ns
mA
A
Microsemi Website - http://www.microsemi.com
Driver Output Characteristics
Symbol
C
out
R
out
L
out
F
MAX
F
MAX
Parameter
Output Capacitance
Output Resistance
Output Inductance
Operating Frequency CL = 3000nF + 50Ω
Operating Frequency RL = 50Ω
30
50
Min
Typ
2500
.8
3
DRF1300(G)
Max
Unit
pF
Ω
nH
MHz
Driver Thermal Characteristics
Symbol
R
θ
JC
R
θ
JHS
T
JSTG
P
DJHS
P
DJC
Parameter
Thermal Resistance Junction to Case
Thermal Resistance Junction to Heat Sink
Storage Temperature
Maximum Power Dissipation @ T
SINK
= 25°C
Total Power Dissipation @ T
C
= 25°C
Min
Typ
1.5
2.5
-55 to 150
Max
Unit
°C/W
°C
W
60
100
MOSFET Absolute Maximum Rating (Per-Section)
Symbol
BV
DSS
I
D
R
DS(on)
T
jmax
Parameter
Drain Source Voltage
Continuous Drain Current T
HS
= 25°C
Drain-Source On State Resistance
Operating Temperature
0.24
175
Min
500
30
Typ
Max
Unit
V
A
Ω
°C
MOSFET Dynamic Characteristics (Per-Section)
Symbol
C
ISS
C
oss
C
rss
Parameter
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Min
Typ
1800
335
75
pF
Max
Unit
MOSFET Thermal Characteristics (Total Package)
Symbol
R
θ
JC
R
θ
JHS
T
JSTG
P
DHS
P
DC
Parameter
Junction to Case Thermal Resistance
Junction to Heat Sink Thermal Resistance
Storage Junction Temperature
Maximum Power Dissipation @ T
SINK
= 25°C
Total Power Dissipation @ T
C
= 25°C
Min
Typ
.06
.140
-55 to 150
Max
Unit
°C/W
°C
KW
1.07
2.5
Section A and B Output Switching Performance
Symbol
T
ON
T
OFF
T
DLY(ON)
T
DLY(OFF)
∆T
DLY(ON)
∆T
DLY(OFF)
050-4971 Rev E 12-2009
Characteristic
Leading Edge 10% to 90%
Trailing Edge 10% to 90%
Total Throughput Delay Time, ON
Total Throughput Delay Time, OFF
Delta T
ON
Delay between Section A and B
Delta T
OFF
Delay between Section A and B
Min
2
45
45
49
-0.5
0
Typ
3
TBD
TBD
50
0
0.6
Max
4
49
47
51
1.5
1.3
Typ
ns
Microsemi reserves the right to change, without notice, the specifications and information contained herein.
DRF1300(G)
Figure 1, DRF1300 Circuit Diagram
The DRF1300 is configured as a Push Pull Hybrid incorporating two independent channels configured with a common source each consisting of a
driver, a high voltage MOSFET and by-pass capacitors. The function of the by-pass capacitors C1 and C2 is to reduce the internal parasitic loop
inductance. This coupled with the tight geometry of the hybrid allows optimal gate drive to the MOSFET. This low parasitic approach coupled
with the Schmitt trigger input (IN), Kelvin signal ground (SG) and the Anti-Ring function; provide improved stability and control in Kilowatt to Multi-
Kilowatt high frequency applications. The IN pin should be referenced to the Kelvin Ground (SG) and is applied to a Schmitt Trigger. The SG
pin is a Kelvin return for the IN pin only. The signal is then applied to the intermediate drivers and level shifters; this section contains proprietary
circuitry designed specifically for ring abatement. To further increase the utility of the device the driver die and the MOSFET die are adjacent die
selected. This provides a very close match in the turn on and propagation delays.
Figure 2, DRF1300 Test Circuit
The test circuit illustrated in Figure 2 was used to evaluate the DRF1300 (available as an evaluation board DRF13XX/EVALSW.) The input
control signal is applied via IN and SG pins using RG188. This provides excellent noise immunity and control of the signal ground currents.
The +V
DD
inputs (pins 2, 6, 8 and 12) should be heavily by-passed by 1uF capacitors as close to the pins as possible. The capacitors used
for this function must be capable of supporting the RMS currents and frequency of the gate load. R
L
set for I
DM
at V
DS
max this load is used to
evaluate the output performance.
050-4971 Rev E 12-2009
DRF1300(G)
Pin Assignments
Pin 1
Pin 2
Pin 3
Pin 4
Pin 5
Pin 6
Pin 7
Pin 8
Pin 9
Pin 10
Pin 11
Pin 12
Pin 13
Pin 14
Pin 15
Pin 16
Pin 17
Pin 18
Ground
U1 +Vdd
U1 FN
U1 IN
U1 SG
U1 +Vdd
Ground
U2 +Vdd
U2 FN
U2 IN
U2 SG
U2 +Vdd
Ground
Source
U2 Drain
Source
U1 Drain
Source
FN (pin 9)
HIGH
HIGH
LOW
LOW
FN (pin 3)
HIGH
HIGH
LOW
LOW
None of the inputs to U1 or U2 of the DRF1300 are isolated for direct connection to a ground referenced power
supply or control circuitry.
Isolation appropriate to the application is the responsibility of the end user.
It
is imperative that high output currents be restricted to the Source (14, 16, 18) and Drain (15, 17) pins by design.
See DRF100 for more information on Driver IC used in the device.
The Function (FN, pin 3 or pin 9) is the invert or non-invert select Pin, it is Internally held high.
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