Document No.: FT_000589
FT313H USB2.0 HS Host Controller Datasheet Version 1.1
Clearance No.: FTDI# 318
Future Technology Devices
International Ltd
.
FT313H
(
USB2.0 HS Embedded Host
Controller)
The FT313H is a Hi-Speed Universal
Serial Bus (USB) Host Controller
compatible with Universal Serial Bus
Specification Rev 2.0 and supports
data transfer speeds of up to 480M
bit/s. The FT313H has the following
advanced features:
Single chip USB2.0 Hi-Speed compatible.
Compatible to Enhanced Host
Interface Specification Rev 1.0.
Controller
Low
power
application.
consumption
for
portable
Supports bus interface I/O voltage from 1.62V
to 3.63V.
Supports hybrid power mode; VCC(3V3) is not
present, VCC(I/O) is powered.
Internal voltage regulator supplies 1.2v to the
digital core.
Supports Battery Charging Specification Rev
1.2.
The downstream port can be configured as
SDP, CDP or DCP.
Supports VBUS power
current control.
switching
and
over
The USB1.1 host is integrated into the USB2.0
EHCI compatible host controller.
Single USB host port.
Supports data transfer at high-speed (480M
bit/s), full-speed (12M bit/s), and low-speed
(1.5M bit/s).
Supports the Isochronous, Interrupt, Control,
and Bulk transfers.
Supports the split transaction for high-speed
Hub and the preamble transaction for full-
speed Hub.
Supports multiple processor interfaces with 8-
bit or 16-bit bus: SRAM, NOR Flash, and
General multiplex.
Single configurable interrupt (INT) line for host
controller.
Integrated 24kB high speed RAM memory.
Supports DMA operation.
Integrated Phase-Locked Loop (PLL) supports
external 12MHz, 19.2MHz, and 24MHz crystal,
and direct external clock source input.
-40°C to 85°C extended operating temperature
range.
Available in compact Pb-free 64 Pin QFN, LQFP
and TQFP packages (all RoHS compliant).
Neither the whole nor any part of the information contained in, or the product described in this manual, may be adapted or reproduced
in any material or electronic form without the prior written consent of the copyright holder. This product and its documentation are
supplied on an as-is basis and no warranty as to their suitability for any particular purpose is either made or implied. Future Technology
Devices International Ltd will not accept any claim for damages howsoever arising as a result of use or failure of this product. Your
statutory rights are not affected. This product or any variant of it is not intended for use in any medical appliance, device or system in
which the failure of the product might reasonably be expected to result in personal injury. This document provides preliminary
information that may be subject to change without notice. No freedom to use patents or other intellectual property rights is implied by
the publication of this document. Future Technology Devices International Ltd,
Unit 1, 2 Seaward Place, Centurion Business Park, Glasgow
G41 1HH
United Kingdom. Scotland Registered Company Number: SC136640
Copyright © 2012 Future Technology Devices International Limited
1
Document No.: FT_000589
FT313H USB2.0 HS Host Controller Datasheet Version 1.1
Clearance No.: FTDI# 318
1
Typical Applications
TV/TV box
Printer
Instrumentation
Media player
Tablet
Set-top box
1.1 Part Numbers
Part Number
Package
FT313HQ-x
FT313HL-x
FT313HP-x
Table 1-1 FT313H Numbers
64 Pin QFN
64 Pin LQFP
64 Pin TQFP
Note: Packaging codes for x is:
-R: Taped and Reel, (QFN is 3000pcs, LQFP is 1000 pcs, TQFP is 2500pcs per reel)
-T: Tray packing, (QFN is 2600pcs, LQFP is 1600 pcs, TQFP is 2500pcs per tray)
For example: FT313HQ-R is 3000 QFN pcs in taped and reel packaging
1.2 USB Compliant
At the time of writing this datasheet, the FT313H was still to complete USB compliance testing.
Copyright © 2012 Future Technology Devices International Limited
2
Document No.: FT_000589
FT313H USB2.0 HS Host Controller Datasheet Version 1.1
Clearance No.: FTDI# 318
2
FT313H Block Diagram
AD[15:0]
A[7:0]
ALE/ADV_N
DMA
Controller
RAM 24KB
VCC(I/O)
X1/CLKIN
X2
CLE
CS_N/CE_N
RD_N/RE_N/
OE_N
WR_N/WE_N
INT
DREQ
MEMORY ARBITER
FT313H
Interface
Control
Logic
PLL
FREQSEL1
FREQSEL2
AGND
EHCI
Compatible
Host Controller
POR
RESET_N
GND
ATX
DACK
VBUS
CPE0
CPE1
REGULATOR
VCC(1V2)
VOUT(1V2)
TESTEN
BCD
VCC(3V3)
OC_N RREF DP
DM AGND PSW_N
Figure 2-1 FT313H Block Diagram
For a description of each function please refer to Section 4.
Copyright © 2012 Future Technology Devices International Limited
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Document No.: FT_000589
FT313H USB2.0 HS Host Controller Datasheet Version 1.1
Clearance No.: FTDI# 318
Table of Contents
1
1.1
1.2
Typical Applications ...................................................................... 2
Part Numbers...................................................................................... 2
USB Compliant .................................................................................... 2
2
3
3.1
3.2
3.3
3.4
FT313H Block Diagram ................................................................. 3
Device Pin Out and Signal Description .......................................... 7
Pin Out – 64pin QFN ........................................................................... 7
Pin Out – 64pin LQFP .......................................................................... 8
Pin Out – 64pin TQFP .......................................................................... 9
Pin Description ................................................................................. 10
4
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
Function Description................................................................... 14
Microcontroller Bus Interface ........................................................... 14
SRAM bus interface mode ................................................................. 15
NOR bus interface mode ................................................................... 16
General multiplex bus interface mode .............................................. 16
Interface mode lock .......................................................................... 16
DMA controller .................................................................................. 16
EHCI host controller ......................................................................... 17
System clock ..................................................................................... 17
Phase Locked Loop (PLL) clock multiplier ...................................................................... 17
4.8.1
4.9
4.9.1
4.9.2
4.9.3
4.9.4
Power management .......................................................................... 18
Power up and reset sequence ...................................................................................... 18
Power supply............................................................................................................. 18
ATX reference voltage ................................................................................................ 18
Power modes ............................................................................................................ 18
4.10
BCD mode ...................................................................................... 19
Overview of registers ....................................................................... 20
EHCI operational registers ................................................................ 21
HCCAPLENGTH register (address = 00h) ....................................................................... 21
HCSPARAMS register (address = 04h) .......................................................................... 21
HCCPARAMS register (address = 08h) .......................................................................... 22
USBCMD register (address = 10h) ............................................................................... 22
USBSTS register (address = 14h) ................................................................................ 24
USBINTR register (address = 18h) ............................................................................... 25
FRINDEX register (address = 1Ch) ............................................................................... 26
PERIODICLISTADDR register (address = 24h) ............................................................... 26
ASYNCLISTADDR register (address = 28h).................................................................... 26
Copyright © 2012 Future Technology Devices International Limited
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5
5.1
5.2
Host controller specific registers ................................................ 20
5.2.1
5.2.2
5.2.3
5.2.4
5.2.5
5.2.6
5.2.7
5.2.8
5.2.9
Document No.: FT_000589
FT313H USB2.0 HS Host Controller Datasheet Version 1.1
Clearance No.: FTDI# 318
5.2.10
POSTSC register (address = 30h) ............................................................................. 27
5.3
5.3.1
5.3.2
5.3.3
5.3.4
5.3.5
5.3.6
5.3.7
5.3.8
5.3.9
Configuration registers ..................................................................... 29
EOTTIME register (address = 34h) ............................................................................... 29
CHIPID register (address = 80h) ................................................................................. 30
HWMODE register (address = 84h) .............................................................................. 30
EDGEINTC register (address = 88h) ............................................................................. 31
SWRESET register (address = 8Ch) .............................................................................. 31
MEMADDR register (address = 90h) ............................................................................. 33
DATAPORT register (address = 92h) ............................................................................ 33
DATASESSION register (address = 94h) ....................................................................... 33
CONFIG register (address = 96h) ................................................................................ 33
AUX_MEMADDR register (address = 98h) .................................................................. 35
AUX_DATAPORT register (address = 9Ah) ................................................................. 35
SLEEPTIMER register (address = 9Ch) ...................................................................... 35
5.3.10
5.3.11
5.3.12
5.4
5.4.1
5.4.2
Interrupt registers ............................................................................ 35
HCINTSTS register (address = A0h) ............................................................................. 35
HCINTEN register (address = A4h)............................................................................... 37
5.5
5.5.1
5.5.2
5.5.3
USB testing registers ........................................................................ 38
TESTMODE register (address = 50h) ............................................................................ 38
TESTPMSET1 register (address = 70h) ......................................................................... 39
TESTPMSET2 register (address = 74h) ......................................................................... 39
6
6.1
6.2
6.3
6.4
Devices Characteristics and Ratings ........................................... 40
Absolute Maximum Ratings............................................................... 40
DC Characteristics............................................................................. 41
AC Characteristics ............................................................................. 44
Timing .............................................................................................. 46
PIO timing ................................................................................................................ 46
DMA timing ............................................................................................................... 52
6.4.1
6.4.2
7
7.1
Application Examples ................................................................. 53
Examples of Bus Interface connection .............................................. 54
16-Bit SRAM asynchronous bus interface ...................................................................... 54
8-Bit SRAM asynchronous bus interface ........................................................................ 54
16-Bit NOR asynchronous bus interface ........................................................................ 55
8-Bit NOR asynchronous bus interface .......................................................................... 55
16-Bit General Multiplex asynchronous bus interface ...................................................... 55
8-Bit General Multiplex asynchronous bus interface ........................................................ 56
7.1.1
7.1.2
7.1.3
7.1.4
7.1.5
7.1.6
8
8.1
8.2
8.3
Package Parameters ................................................................... 57
QFN-64 Package Dimensions ............................................................ 57
LQFP-64 Package Dimensions ........................................................... 58
TQFP-64 Package Dimensions ........................................................... 59
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