®
SP9604
Quad, 12–Bit, Low Power Voltage
Output D/A Converter
s
s
s
s
s
s
s
s
s
s
s
Low Cost
Four 12–Bit DAC’s on a Single Chip
Very Low Power — 30 mW (8mW/DAC)
Double-Buffered Inputs
+ 5V Supply Operation
Voltage Outputs, + 4.5V Range
Midscale Preset, Zero Volts Out
Guaranteed +0.5 LSB Max INL
Guaranteed +0.75 LSB Max DNL
250kHz 4-Quadrant Multiplying Bandwidth
28–pin SOIC and Plastic DIP
Packages
s
Either 12 or 8 bit
µP
bus
DESCRIPTION
The
SP9604
is a very low power replacement for the popular SP9345, Quad 12-Bit Digital-to-
Analog Converter. It features
±4.5V
output swings when using
±5
volt supplies. The converter
is double-buffered for easy microprocessor interface. Each 12-bit DAC is independently
addressable and all DACs may be simultaneously updated using a single transfer command. The
output settling-time is specified at 30µs. The
SP9604
is available in 28–pin SOIC and plastic DIP
packages, specified over commercial temperature range.
Ref In
INPUT
REGISTERS
DATA
INPUTS
8 MSB's
4 LSB's
LATCH
LATCH
DAC
REGISTERS
–
LATCH
DAC
+
VOUT1
–
LATCH
DAC
+
VOUT2
–
LATCH
LATCH
DAC
+
VOUT3
–
LATCH
LATCH
DAC
+
VOUT4
CONTROL LOGIC
A0
A1
CS
WR1 B1/B2 WR2 XFER CLR
SP9604DS/03
SP9604 Quad, 12-Bit, Low Power Voltage Output D/A Converter
© Copyright 2000 Sipex Corporation
1
ABSOLUTE MAXIMUM RATINGS
These are stress ratings only and functional operation of the device
at these or any other above those indicated in the operation
sections of the specifications below is not implied. Exposure to
absolute maximum rating conditions for extended periods of time
may affect reliability.
V
DD
- GND ..................................................................... -0.3V,+6.0V
V
SS
- GND .................................................................... +0.3V, -6.0V
V
DD
- V
SS ......................................................................................................................
-0.3V, +12.0V
V
REF
..................................................................................... V
SS
, V
DD
D
IN
....................................................................................... V
SS
, V
DD
Power Dissipation
Plastic DIP .......................................................................... 375mW
(derate 7mW/°C above +70°C)
Small Outline ...................................................................... 375mW
(derate 7mW/˚C above +70˚C)
SPECIFICATIONS
(Typical @ 25˚C, T
MIN
≤
T
A
≤T
MAX
; V
DD
= +5V, V
SS
= -5V, V
REF
= +3V; CMOS logic level digital inputs; specifications apply to all grades unless otherwise noted.)
PARAMETER
DIGITAL INPUTS
Logic Levels
V
V
4 Quad, Bipolar Coding
REFERENCE INPUT
Voltage Range
Input Resistance
ANALOG OUTPUT
Gain
-K
-J
IH
IL
MIN.
TYP.
MAX.
UNITS
CONDITIONS
2.4
0.8
Offset Binary
+3
2.2
+4.5
Volts
Volts
1.5
Volts
kΩ
Note 5
D = 1,877; code dependent
IN
Initial Offset Bipolar
Voltage Range Bipolar
Output Current
STATIC PERFORMANCE
Resolution
Integral Linearity
-K
-J
Differential Linearity
-K
-J
Monotonicity
DYNAMIC PERFORMANCE
Settling Time
Small Signal
Full Scale
Slew Rate
Multiplying Bandwidth
+0.5
+1.0
+1.0
+0.25
+3.0
+5.0
+0.5
12
+0.25
+0.5
+0.5
+2.0
+4.0
+5.0
+3.0
+4.5
LSB
LSB
LSB
LSB
Volts
mA
mA
Bits
V
V
V
D
REF
REF
REF
IN
= +3V; Note 3
= +3V; Note 3
= +4.5V; Note 3
= 2,048
V = +3V
V = +4.5V
REF
REF
+0.5
+1.0
+3.0
LSB
LSB
LSB
LSB
LSB
V = +3V; Note 3
V = +3V; Note 3
V = +4.5V; Note 3
REF
REF
REF
+0.25
+0.75
+0.25
+1.0
Guaranteed
4
30
0.3
250
µs
µs
V/µs
KHz
to 0.024%
to 0.024%
SP9604DS/03
SP9604 Quad, 12-Bit, Low Power Voltage Output D/A Converter
© Copyright 2000 Sipex Corporation
2
SPECIFICATIONS
(continued)
(Typical @ 25˚C, T
MIN
≤
T
A
≤T
MAX
; V
DD
= +5V, V
SS
= -5V, V
REF
= +3V; CMOS logic level digital inputs; specifications apply to all grades unless otherwise noted.)
PARAMETER
MIN.
TYP.
MAX.
STABILITY
Gain
15
Bipolar Zero
15
SWITCHING CHARACTERISTICS
t
DS
Data Set Up Time
140
100
t
DN
Data Hold Time
0
t
WR
Write Pulse Width
140
100
t
XFER
Transfer Pulse Width
140
100
t
WC
Total Write Command
280
200
POWER REQUIREMENTS
V
DD
–J, –K
3
4
V
SS
–J, –K
3
4
Power Dissipation
30
ENVIRONMENTAL AND MECHANICAL
Operating Temperature
-J, -K
0
+70
Storage
-60
+150
Package
-_P
28-pin Plastic DIP
-_S
28-pin SOIC
Notes:
1.
2.
3.
4.
5.
UNITS
ppm/˚C
ppm/˚C
ns
ns
ns
ns
ns
CONDITIONS
t to t
t to t
MIN
MIN
MAX
MAX
to rising edge of WR1
Figure 4
Note 5
+5V, +3%; Note 4, 5
mA
-5V, +3%; Note 4, 5
mA
mW
°C
°C
Integral Linearity, for the
SP9604,
is measured as the arithmetic mean value of the magnitudes of
the greatest positive deviation and the greatest negative deviation from the theoretical value for any
given input condition.
Differential Linearity is the deviation of an output step from the theoretical value of 1 LSB for any two
adjacent digital input codes.
1 LSB = 2*V
REF
/4,096.
V
REF
= 0V.
The following power up sequence is recommended to avoid latch up: V
SS
(-5V), V
DD
(+5V), REF IN.
+0.25 lsb
DNLE
-0.25 lsb
+0.25 lsb
INLE
-0.25 lsb
0
DNLE, INLE Plots
CODE
4095
SP9604DS/03
SP9604 Quad, 12-Bit, Low Power Voltage Output D/A Converter
© Copyright 2000 Sipex Corporation
3
PIN ASSIGNMENTS
Pin 1 — V
OUT 4
— Voltage Output from DAC4.
Pin 2 — V
SS
— –5V Power Supply Input.
Pin 3 — V
DD
— +5V Power Supply Input.
Pin 4 — CLR — Clear. Gated with WR2 (pin 11).
Active low. Clears all DAC outputs to 0V.
Pin 5 — REF IN — Reference Input for DACs.
Pin 6 — GND — Ground.
Pin 7 — B1/B2 — Byte 1/Byte 2 — Selects Data
Input Format. A logic “1” on pin 7 selects the 12–bit
mode, and all 12 data bits are presented to the DAC(s)
unchanged; a logic “0” selects the 8–bit mode, and the
four LSBs are connected to the four MSBs, allowing
an 8–bit MSB–justified interface.
Pins 8 and 9 — A
0
& A
1
— Address for DAC
Selection. A
1
/A
0
= 0/0 = DAC1; 0/1 = DAC2; 1/0 =
DAC3; 1/1 = DAC4.
Pin 10 — XFER — Transfer. Gated with WR2 (pin
11); loads all DAC registers simultaneously. Active
low.
Pin 11 — WR2 — Write Input 2 — In conjunction
with XFER (pin 10), controls the transfer of data
from the input registers to the DAC registers. In
conjunction with CLR (pin 4), the DAC registers are
forced to 1000 0000 0000 and the DAC outputs will
settle to 0V. Active low.
Pin 12 — WR1 — Write Input1 — In conjunction
with CS (pin 13), enables input register selection, and
controls the transfer of data from the input bus to the
input registers. Active low.
Pin 13 — CS — Chip Select — Enables writing data
to input registers and/or transferring data from input
bus to DAC registers. Active low.
PINOUT — 28–PIN PLASTIC DIP & SOIC
V
OUT4
V
SS
V
DD
CLR
REF IN
GND
B1/B2
A
0
A
1
XFER
WR2
WR1
CS
V
OUT1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
SP9604
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
OUT3
DB
0
DB
1
DB
2
DB
3
DB
4
DB
5
DB
6
DB
7
DB
8
DB
9
DB
10
DB
11
V
OUT2
Pin 14 — V
OUT1
— Voltage Output from DAC1.
Pin 15 — V
OUT2
— Voltage Output from DAC2.
Pin 16 — DB
11
— Data Bit 11; Most Significant Bit.
Pin 17 — DB
10
— Data Bit 10.
Pin 18 — DB
9
— Data Bit 9.
Pin 19 — DB
8
— Data Bit 8.
Pin 20 — DB
7
— Data Bit 7.
Pin 21 — DB
6
— Data Bit 6.
Pin 22 — DB
5
— Data Bit 5.
Pin 23 — DB
4
— Data Bit 4.
Pin 24 — DB
3
— Data Bit 3.
Pin 25 — DB
2
— Data Bit 2.
Pin 26 — DB
1
— Data Bit 1.
Pin 27 — DB
0
— Data Bit 0; LSB
Pin 28 — V
OUT3
— Voltage Output from DAC3.
SP9604DS/03
SP9604 Quad, 12-Bit, Low Power Voltage Output D/A Converter
© Copyright 2000 Sipex Corporation
4
FEATURES
The
SP9604
is a low–power replacement for the
popular SP9345, Quad 12-Bit Digital-to-Analog Con-
verter. This Quad, Voltage Output, 12-Bit Digital-to-
Analog Converter features
±4.5V
output swings
when using
±5
volt supplies. The input coding format
used is standard offset binary. (Please refer to
Table 1.)
The converter utilizes double-buffering on each of the
12 parallel digital inputs, for easy microprocessor
interface. Each 12-bit DAC is independently addres-
sable and all DACs may be simultaneously updated
using a single XFER command. The output settling-
time is specified at 30µs to full 12–bit accuracy when
driving a 5Kohm, 50pf load combination. The
SP9604,
Quad 12-Bit Digital-to-Analog Converter is
ideally suited for applications such as ATE, process
controllers,robotics,andinstrumentation. The
SP9604
is available in 28–pin plastic DIP or SOIC packages,
specified over the commercial (0°C to +70°C)
temperature range.
using the CS signal in both modes. The digital inputs
are designed to be both TTL and 5V CMOS compat-
ible.
In order to reduce the DAC full scale output sensitivity
to the large weighting of the MSB’s found in conven-
tional R-2R resistor ladders, the 3 MSB’s are decoded
into 8 equally weighted levels. This reduces the
contribution of each bit by a factor of 4, thus, reducing
the output sensitivity to mis–matches in resistors and
switches by the same amount. Linearity errors and
stability are both improved for the same reasons.
Each D/A converter is separated from the data bus by
two registers, each consisting of level-triggered
latches,
Figure 1.
The first register (input register) is
12-bits wide. The input register is selected by the
address input A
0
and A
1
and is enabled by the CS and
WR1 signals. In the 8-bit mode, the enable signal to
the 8 MSB’s is disabled by a logic low on B1/B2 to
allow the 4 LSB’s to be updated. The second register
(DAC register), accepts the decoded 3 MSB’s plus the
9 LSB’s. The four DAC registers are updated simul-
taneously for all DAC’s using the XFER and WR2
signals. Using the CLR and WR2 signals or the
power-on-reset, (enabled when the power is switched
on) the DAC registers are set to 1000 0000 0000 and
the DAC outputs will settle to 0V.
Using the control logic inputs, the user has full control
of address decoding, chip enable, data transfer and
clearing of the DAC’s. The control logic inputs are
level triggered, and like the data inputs, are TTL and
CMOS compatible. The truth table (Table
2)
shows
the appropriate functions associated with the states of
the control logic inputs.
The DACs themselves are implemented with a preci-
sion thin–film resistor network and CMOS transmis-
sion gate switches. Each D/A converter is used to
convert the 12–bit input from its DAC register to a
precision voltage.
The bipolar voltage output of the
SP9604
is created
on-chip from the DAC Voltage Output (V
DAC
) by
using an operational amplifier and two feedback
resistors connected as shown in
Figure 2.
This configuration produces a
±4.5V
bipolar
output range with standard offset binary coding.
THEORY OF OPERATION
The
SP9604
consists of five main functional blocks
— input data multiplexer, data registers, control logic,
four 12-bit D/A converters, and four bipolar output
voltage amplifiers. The input data multiplexer is
designed to interface to either 12- or 8-bit micropro-
cessor data busses. The input data format is controlled
by the B1/B2 signal — a logic “1” selects the 12-bit
mode, while a logic “0” selects the 8-bit mode. In the
12-bit mode the data is transferred to the input registers
without changes in its format. In the 8-bit mode, the
four least significant bits (LSBs) are connected to the
four most significant bits (MSBs), allowing an 8-bit
MSB-justified interface. All data inputs are enabled
INPUT
MSB
1111
1111
1000
1000
0000
0000
1111
1111
0000
0000
0000
0000
LSB
1111
1110
0001
0000
0001
0000
1 LSB =
Table 1. Offset Binary Coding
2
12
VREF - 1 LSB
VREF - 2 LSB
0 + 1 LSB
0
-VREF + 1 LSB
-VREF
2V
REF
OUTPUT
SP9604DS/03
SP9604 Quad, 12-Bit, Low Power Voltage Output D/A Converter
© Copyright 2000 Sipex Corporation
5
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