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LTC2151CUJ-12#TRPBF

Description
1-Channel Single ADC Pipelined 210Msps 12-bit Parallel 40-Pin QFN EP T/R
File Size717KB,30 Pages
ManufacturerADI
Websitehttps://www.analog.com
Download Datasheet Parametric View All

LTC2151CUJ-12#TRPBF Overview

1-Channel Single ADC Pipelined 210Msps 12-bit Parallel 40-Pin QFN EP T/R

LTC2151CUJ-12#TRPBF Parametric

Parameter NameAttribute value
EU restricts the use of certain hazardous substancesCompliant
ECCN (US)3A991.c.2
Part StatusActive
HTS8542.39.00.01
Converter TypeGeneral Purpose
ArchitecturePipelined
Resolution12bit
Number of ADCs1
Number of Input Channels1
Sampling Rate210Msps
Digital Interface TypeParallel|LVDS
Input TypeVoltage
Input Signal TypeDifferential
Voltage ReferenceInternal|External
Voltage Supply SourceSingle
Input Voltage1.5Vp-p
Minimum Single Supply Voltage (V)1.7
Typical Single Supply Voltage (V)1.8
Maximum Single Supply Voltage (V)1.9
Typical Power Dissipation (mW)364
Maximum Power Dissipation (mW)405
Integral Nonlinearity Error±1.2LSB
Full Scale Error-4/3%FSR
Signal to Noise Ratio68.5dBFS(Typ)
No Missing Codes (bit)12
Sample and HoldYes
Single-Ended InputNo
Digital Supply SupportNo
Minimum Operating Temperature (°C)0
Maximum Operating Temperature (°C)70
PackagingTape and Reel
Supplier Temperature GradeCommercial
Supplier PackageQFN EP
Pin Count40
Standard Package NameQFN
MountingSurface Mount
Package Height0.75(Max)
Package Length6
Package Width6
PCB changed40
Lead ShapeNo Lead
LTC2152-12/
LTC2151-12/LTC2150-12
Single 12-Bit 250Msps/
210Msps/170Msps ADCs
FEATURES
n
n
n
n
n
n
n
n
n
n
n
n
DESCRIPTION
The
LTC
®
2152-12/LTC2151-12/LTC2150-12
are a family
of 250Msps/210Msps/170Msps 12-bit A/D converters
designed for digitizing high frequency, wide dynamic range
signals. They are perfect for demanding communications
applications with AC performance that includes 68.5dB
SNR and 90dB spurious free dynamic range (SFDR). The
1.25GHz input bandwidth allows the ADC to undersample
high input frequencies with good performance. The latency
is only six clock cycles.
DC specs include ±0.26LSB INL (typ), ±0.16LSB DNL (typ)
and no missing codes over temperature. The transition
noise is 0.54LSB
RMS
.
The digital outputs are double-data rate (DDR) LVDS.
The ENC
+
and ENC
inputs can be driven differentially with
a sine wave, PECL, LVDS, TTL, or CMOS inputs. An optional
clock duty cycle stabilizer allows high performance at full
speed for a wide range of clock duty cycles.
L,
LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
68.5dB SNR
90dB SFDR
Low Power: 347mW/333mW/306mW Total
Single 1.8V Supply
DDR LVDS Outputs
Easy-to-Drive 1.5V
P-P
Input Range
1.25GHz Full Power Bandwidth S/H
Optional Clock Duty Cycle Stabilizer
Low Power Sleep and Nap Modes
Serial SPI Port for Configuration
Pin-Compatible 14-Bit Versions
40-Lead (6mm × 6mm) QFN Package
Communications
Cellular Basestations
Software Defined Radios
Medical Imaging
High Definition Video
Testing and Measurement Instruments
APPLICATIONS
n
n
n
n
n
n
TYPICAL APPLICATION
V
DD
OV
DD
D10_11
D0_1
0
–20
AMPLITUDE (dBFS)
DDR
LVDS
–40
–60
–80
LTC2152-12: 32K Point 2-Tone FFT,
f
IN
= 71MHz and 69MHz, 250Msps
ANALOG
INPUT
S/H
12-BIT
PIPELINED
ADC
CORRECTION
LOGIC
OUTPUT
DRIVERS
CLOCK
CLOCK/DUTY
CYCLE
CONTROL
21521012 TA01a
OGND
–100
–120
GND
0
20
40
60
80
100
FREQUENCY (MHz)
120
21521012 TA01b
21521012fa
For more information
www.linear.com/LTC2152-12
1
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