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LTC2156CUP-14#PBF

Description
2-Channel Dual ADC Pipelined 210Msps 14-bit Parallel 64-Pin QFN EP Tube
File Size1MB,34 Pages
ManufacturerADI
Websitehttps://www.analog.com
Download Datasheet Parametric View All

LTC2156CUP-14#PBF Overview

2-Channel Dual ADC Pipelined 210Msps 14-bit Parallel 64-Pin QFN EP Tube

LTC2156CUP-14#PBF Parametric

Parameter NameAttribute value
EU restricts the use of certain hazardous substancesCompliant
ECCN (US)3A991.c.3
Part StatusActive
HTS8542.39.00.01
Converter TypeGeneral Purpose
ArchitecturePipelined
Resolution14bit
Number of ADCs2
Number of Input Channels2
Sampling Rate210Msps
Digital Interface TypeParallel|LVDS
Input TypeVoltage
Input Signal TypeDifferential
Voltage ReferenceExternal|Internal
Voltage Supply SourceSingle
Input Voltage1.5Vp-p
Minimum Single Supply Voltage (V)1.7
Typical Single Supply Voltage (V)1.8
Maximum Single Supply Voltage (V)1.9
Typical Power Dissipation (mW)670
Maximum Power Dissipation (mW)745
Integral Nonlinearity Error±5.3LSB
Full Scale Error-4/2.2%FSR
Signal to Noise Ratio70dBFS(Typ)
No Missing Codes (bit)14
Sample and HoldYes
Single-Ended InputNo
Digital Supply SupportNo
Minimum Operating Temperature (°C)0
Maximum Operating Temperature (°C)70
PackagingTube
Supplier Temperature GradeCommercial
Supplier PackageQFN EP
Pin Count64
Standard Package NameQFN
MountingSurface Mount
Package Height0.75(Max)
Package Length9
Package Width9
PCB changed64
Lead ShapeNo Lead
LTC2157-14/
LTC2156-14/LTC2155-14
Dual 14-Bit 250Msps/
210Msps/170Msps ADCs
FEATURES
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DESCRIPTION
The
LTC
®
2157-14/LTC2156-14/LTC2155-14
are 2-channel
simultaneous sampling 250Msps/210Msps/170Msps
14-bit A/D converters designed for digitizing high fre-
quency, wide dynamic range signals. They are perfect
for demanding communications applications with AC
performance that includes 70dB SNR and 90dB spurious
free dynamic range (SFDR). The 1.25GHz input bandwidth
allows the ADC to undersample high frequencies with
good performance. The latency is only six clock cycles.
DC specs include ±0.85LSB INL (typ), ±0.25LSB DNL (typ)
and no missing codes over temperature. The transition
noise is 1.82LSB
RMS
.
The digital outputs are double data rate (DDR) LVDS.
The ENC
+
and ENC
inputs can be driven differentially with
a sine wave, PECL, LVDS, TTL, or CMOS inputs. An optional
clock duty cycle stabilizer allows high performance at full
speed for a wide range of clock duty cycles.
L,
LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
70dB SNR
90dB SFDR
Low Power: 650mW/616mW/567mW Total
Single 1.8V Supply
DDR LVDS Outputs
Easy-to-Drive 1.5V
P-P
Input Range
1.25GHz Full Power Bandwidth S/H
Optional Clock Duty Cycle Stabilizer
Low Power Sleep and Nap Modes
Serial SPI Port for Configuration
Pin-Compatible 12-Bit Versions
64-Pin (9mm × 9mm) QFN Package
APPLICATIONS
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Communications
Cellular Basestations
Software Defined Radios
Medical Imaging
High Definition Video
Testing and Measurement Instruments
TYPICAL APPLICATION
V
DD
CHANNEL A
ANALOG
INPUT
14-BIT
PIPELINED
ADC CORE
CORRECTION
LOGIC
OUTPUT
DRIVERS
OV
DD
DA12_13
DA0_1
0
DDR
LVDS
AMPLITUDE (dBFS)
DDR
LVDS
–20
–40
–60
–80
LTC2157-14 32K Point FFT,
f
IN
= 15MHz, –1dBFS, 250Msps
S/H
CLOCK
CLOCK/DUTY
CYCLE
CONTROL
OGND
CHANNEL B
OV
DD
–100
ANALOG
INPUT
14-BIT
PIPELINED
ADC CORE
GND
21576514 TA01
S/H
CORRECTION
LOGIC
OUTPUT
DRIVERS
DB12_13
DB0_1
–120
0
20
40
60
80
100
FREQUENCY (MHz)
120
21576514 TA01b
OGND
21576514fb
For more information
www.linear.com/LTC2157-14
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