EEWORLDEEWORLDEEWORLD

Part Number

Search

LTC2165IUK#TRPBF

Description
1-Channel Single ADC Pipelined 125Msps 16-bit Parallel 48-Pin QFN EP T/R
File Size681KB,36 Pages
ManufacturerADI
Websitehttps://www.analog.com
Download Datasheet Parametric View All

LTC2165IUK#TRPBF Overview

1-Channel Single ADC Pipelined 125Msps 16-bit Parallel 48-Pin QFN EP T/R

LTC2165IUK#TRPBF Parametric

Parameter NameAttribute value
EU restricts the use of certain hazardous substancesCompliant
ECCN (US)3A001.a.5.a.5
Part StatusActive
HTS8542.39.00.01
Converter TypeGeneral Purpose
ArchitecturePipelined
Resolution16bit
Number of ADCs1
Number of Input Channels1
Sampling Rate125Msps
Digital Interface TypeParallel
Input TypeVoltage
Input Signal TypeSingle-Ended|Differential
Voltage ReferenceInternal|External
Voltage Supply SourceSingle
Input Voltage1Vp-p/2Vp-p
Minimum Single Supply Voltage (V)1.7
Typical Single Supply Voltage (V)1.8
Maximum Single Supply Voltage (V)1.9
Typical Power Dissipation (mW)279
Maximum Power Dissipation (mW)314
Integral Nonlinearity Error±6LSB
Full Scale Error-1.8/0.7%FSR
Signal to Noise Ratio76.8dBFS(Typ)
No Missing Codes (bit)16
Sample and HoldYes
Single-Ended InputYes
Digital Supply SupportNo
Minimum Operating Temperature (°C)-40
Maximum Operating Temperature (°C)85
PackagingTape and Reel
Supplier PackageQFN EP
Pin Count48
Standard Package NameQFN
MountingSurface Mount
Package Height0.75(Max)
Package Length7
Package Width7
PCB changed48
Lead ShapeNo Lead
LTC2165/LTC2164/LTC2163
16-Bit, 125/105/80Msps
Low Power ADCs
FeaTures
n
n
n
n
n
n
n
n
n
n
n
n
DescripTion
The LTC
®
2165/LTC2164/LTC2163 are sampling 16-bit A/D
converters designed for digitizing high frequency, wide
dynamic range signals. They are perfect for demanding
communications applications with AC performance that
includes 76.8dB SNR and 90dB spurious free dynamic
range (SFDR). Ultralow jitter of 0.07ps
RMS
allows unders-
ampling of IF frequencies with excellent noise performance.
DC specs include ±2LSB INL (typ), ±0.5LSB DNL (typ)
and no missing codes over temperature. The transition
noise is 3.4LSB
RMS
.
The digital outputs can be either full rate CMOS, double
data rate CMOS, or double data rate LVDS. A separate
output power supply allows the CMOS output swing to
range from 1.2V to 1.8V.
The ENC
+
and ENC
inputs may be driven differentially
or single-ended with a sine wave, PECL, LVDS, TTL, or
CMOS inputs. An optional clock duty cycle stabilizer al-
lows high performance at full speed for a wide range of
clock duty cycles.
L,
LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
76.8dB SNR
90dB SFDR
Low Power: 194mW/163mW/108mW
Single 1.8V Supply
CMOS, DDR CMOS, or DDR LVDS Outputs
Selectable Input Ranges: 1V
P-P
to 2V
P-P
550MHz Full Power Bandwidth S/H
Optional Data Output Randomizer
Optional Clock Duty Cycle Stabilizer
Shutdown and Nap Modes
Serial SPI Port for Configuration
48-Pin (7mm
×
7mm) QFN Package
applicaTions
n
n
n
n
n
n
Communications
Cellular Base Stations
Software Defined Radios
Portable Medical Imaging
Multichannel Data Acquisition
Nondestructive Testing
Typical applicaTion
1.8V
V
DD
1.8V
OV
DD
2-Tone FFT, f
IN
= 70MHz and 69MHz
0
–10
–20
–30
AMPLITUDE (dBFS)
–40
–50
–60
–70
–80
D15
D0
ANALOG
INPUT
S/H
16-BIT
ADC CORE
OUTPUT
DRIVERS
CMOS, DDR
CMOS OR
DDR LVDS
OUTPUTS
125MHz
CLOCK
CLOCK
CONTROL
–90
–100
–110
–120
0
10
20
30
40
FREQUENCY (MHz)
50
60
2165 TA01b
2165 TA01a
GND
OGND
216543f
1
SDRAM Controller
I'm writing a DRAM controller recently. Is there any expert who can share his experience or send me some information? Thank you....
w_alex FPGA/CPLD
How to configure GPIO in halt() mode?
In halt() mode, how to configure GPIO to save power consumption,GPIO_Init(GPIOC, GPIO_Pin_All,GPIO_Mode_In_PU_No_IT); I have configured GPIO and measured the pin and found that it is always at a high ...
woinwow stm32/stm8
FPGA Prototyping: Software is the Key
...
FPGA小牛 FPGA/CPLD
Max8860 cannot adjust output voltage
The 2440 board I bought last time uses MAX8860 to output 1.25v voltage. The model I purchased is max8860eua18+. Connect as shown below, and the output is fixed at 1.83v. I don't know why. Has anyone e...
chenzhufly ARM Technology
How to read a line of text in EVC4
I open a very large text file and need to display it in pages. What should I do? I want to read the number of lines that can be displayed first (for example, 5 lines), and then display the next 5 line...
wuyusiwei Embedded System
The most basic of the basics...voltage divider circuit
The most commonly used voltage division calculation in design.. Since I am self-taught, my level is very low.. I often forget, so I made a file to help me remember... Haha, one attachment is too small...
pywmiss Analog electronics

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 1303  245  2303  2766  753  27  5  47  56  16 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号