16-bit A/D converter designed for digitizing high frequency,
wide dynamic range signals. It is perfect for demanding
communications applications with AC performance that
includes 84.1dB SNR and 99dB spurious free dynamic
range (SFDR).
DC specs include ±1LSB INL (typ), ±0.2LSB DNL (typ)
and no missing codes over temperature. The transition
noise is 1.44LSB
RMS
.
To minimize the number of data lines the digital outputs
are serial LVDS. Each channel outputs one bit, two bits or
four bits at a time. The LVDS drivers have optional internal
termination and adjustable output levels to ensure clean
signal integrity.
The ENC
+
and ENC
–
inputs may be driven differentially or
single ended with a sine wave, PECL, LVDS, TTL or CMOS
inputs. An internal clock duty cycle stabilizer allows high
performance at full speed for a wide range of clock duty
cycles.
L,
LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
2-Channel Simultaneous Sampling ADC
Serial LVDS Outputs: 1, 2 or 4 Bits per Channel
84.1dB SNR (46μV
RMS
Input Referred Noise)
99dB SFDR
Low Power: 185mW Total
92mW per Channel
Single 1.8V Supply
Selectable Input Ranges: 1V
P-P
to 2.1V
P-P
200MHz Full-Power Bandwidth S/H
Shutdown and Nap Modes
Serial SPI Port for Configuration
Pin Compatible With
LTC2190: 16-Bit, 25Msps, 104mW
52-Lead (7mm
×
8mm) QFN Package
APPLICATIONS
n
n
n
n
Low Power Instrumentation
Software-Defined Radios
Portable Medical Imaging
Multi-Channel Data Acquisition
TYPICAL APPLICATION
Integral Non-Linearity (INL)
1.8V
V
DD
CH1
ANALOG
INPUT
CH2
ANALOG
INPUT
ENCODE
INPUT
16-BIT
ADC CORE
1.8V
OV
DD
1.5
S/H
OUT1A
OUT1B
OUT1C
OUT1D
OUT2A
OUT2B
OUT2C
OUT2D
DATA CLOCK OUT
FRAME
1.0
INL ERROR (LSB)
0.5
0.0
–0.5
–1.0
–1.5
–2.0
0
16384
32768
49152
OUTPUT CODE
65536
2271 TA02
2.0
S/H
16-BIT
ADC CORE
DATA
SERIALIZER
SERIALIZED
LVDS
OUTPUTS
PLL
GND
OGND
2271 TA01
2271f
1
LTC2271
ABSOLUTE MAXIMUM RATINGS
(Notes 1, 2)
PIN CONFIGURATION
TOP VIEW
OUT1A
+
OUT1A
–
OUT1B
+
OUT2C
–
OUT1B
–
40 OUT1C
+
39 OUT1C
–
38 OUT1D
+
37 OUT1D
–
36 DCO
+
35 DCO
–
53
GND
34 OV
DD
33 OGND
32 FR
+
31 FR–
30 OUT2A
+
29 OUT2A
–
28 OUT2B
+
27 OUT2B
–
15 16 17 18 19 20 21 22 23 24 25 26
ENC
+
ENC
–
–
Supply Voltages
V
DD
, OV
DD
................................................ –0.3V to 2V
Analog Input Voltage
A
IN
+, A
IN
–, PAR/SER, SENSE
(Note 3) ....................................–0.3V to (V
DD
+ 0.2V)
Digital Input Voltage
ENC
+
, ENC
–
,
CS,
SDI, SCK (Note 4) ...... –0.3V to 3.9V
SDO (Note 4) ............................................ –0.3V to 3.9V
Digital Output Voltage ................ –0.3V to (OV
DD
+ 0.3V)
Operating Temperature Range
LTC2271C ................................................ 0°C to 70°C
LTC2271I.............................................. –40°C to 85°C
Storage Temperature Range................... –65°C to 150°C
SENSE
V
REF
GND
GND
52 51 50 49 48 47 46 45 44 43 42 41
V
CM1
1
GND 2
A
IN1+
3
A
IN1–
4
GND 5
REFH 6
REFL 7
REFH 8
REFL 9
PAR/SER 10
A
IN2+
11
A
IN2–
12
GND 13
V
CM2
14
OUT2D
+
OUT2C
+
CS
SCK
V
DD
V
DD
SDI
GND
GND
SDO
V
DD
V
DD
UKG PACKAGE
52-LEAD (7mm 8mm) PLASTIC QFN
T
JMAX
= 150°C,
θ
JA
= 29°C/W
EXPOSED PAD (PIN 53) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH
LTC2271CUKG#PBF
LTC2271IUKG#PBF
TAPE AND REEL
LTC2271CUKG#TRPBF
LTC2271IUKG#TRPBF
PART MARKING*
LTC2271UKG
LTC2271UKG
PACKAGE DESCRIPTION
52-Lead (7mm
×
8mm) Plastic QFN
52-Lead (7mm
×
8mm) Plastic QFN
TEMPERATURE RANGE
0°C to 70°C
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to:
http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to:
http://www.linear.com/tapeandreel/
OUT2D
2271f
2
LTC2271
CONVERTER CHARACTERISTICS
PARAMETER
Resolution (No Missing Codes)
Integral Linearity Error
Differential Linearity Error
Offset Error
Gain Error
Offset Drift
Full-Scale Drift
Gain Matching
Offset Matching
Transition Noise
Internal Reference
External Reference
l
l
The
l
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25°C. (Note 5)
CONDITIONS
l
MIN
16
–2.6
–0.8
–7
–1.6
l
l
l
l
TYP
±1
±0.2
±1.3
±1.2
–0.3
±10
±30
±10
MAX
2.6
0.8
7
1
UNITS
Bits
LSB
LSB
mV
%FS
%FS
μV/°C
ppm/°C
ppm/°C
Differential Analog Input (Note 6)
Differential Analog Input
(Note 7)
Internal Reference
External Reference
–0.2
–10
±0.06
±1.5
1.44
0.2
10
%FS
mV
LSB
RMS
ANALOG INPUT
The
l
denotes the specifications which apply over the full operating temperature range, otherwise
specifications are at T
A
= 25°C. (Note 5)
PARAMETER
Analog Input Range (A
IN
+ – A
IN
–)
Analog Input Common Mode (A
IN
+ + A
IN
–)/2
Analog Input Common Mode Current
Analog Input Leakage Current (No Encode)
PAR/SER Input Leakage Current
SENSE Input Leakage Current
Sample-and-Hold Acquisition Delay Time
Sample-and-Hold Acquisition Delay Jitter
Analog Input Common Mode Rejection Ratio
Full-Power Bandwidth
Figure 5 Test Circuit
Single-Ended Encode
Differential Encode
SYMBOL
V
IN
V
IN(CM)
V
SENSE
I
INCM
I
IN1
I
IN2
I
IN3
t
AP
t
JITTER
CMRR
BW–3B
CONDITIONS
1.7V < V
DD
< 1.9V
Differential Analog Input (Note 8)
Per Pin, 20Msps
0 < A
IN
+, A
IN
– < V
DD
0 < PAR/SER < V
DD
0.625V < SENSE < 1.3V
l
l
l
l
l
l
MIN
0.65
0.625
–1
–1
–2
TYP
1 to 2.1
V
CM
1.250
32
MAX
V
CM
+ 200mV
1.300
1
1
2
UNITS
V
P-P
V
V
μA
μA
μA
μA
ns
fs
RMS
fs
RMS
dB
MHz
External Voltage Reference Applied to SENSE External Reference Mode
0
85
100
80
200
2271f
3
LTC2271
DYNAMIC ACCURACY
SYMBOL
SNR
PARAMETER
Signal-to-Noise Ratio
The
l
denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at T
A
= 25°C. A
IN
= –1dBFS. (Note 5)
CONDITIONS
1.4MHz Input
5MHz Input
30MHz Input
70MHz Input
1.4MHz Input
5MHz Input
30MHz Input
70MHz Input
1.4MHz Input
5MHz Input
30MHz Input
70MHz Input
1.4MHz Input
5MHz Input
30MHz Input
70MHz Input
1.4MHz Input
5MHz Input
30MHz Input
70MHz Input
10MHz Input
l
MIN
82.3
TYP
84.1
84.1
83.8
82.7
99
98
98
90
99
98
98
96
110
110
105
100
83.9
83.9
83.7
82.0
–110
MAX
UNITS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBc
SFDR
Spurious Free Dynamic Range, 2nd Harmonic
l
88
Spurious Free Dynamic Range, 3rd Harmonic
l
88
Spurious Free Dynamic Range, 4th Harmonic or Higher
l
93
S/(N+D)
Signal-to-Noise Plus Distortion Ratio
l
81.8
Crosstalk
INTERNAL REFERENCE CHARACTERISTICS
PARAMETER
V
CM
Output Voltage
V
CM
Output Temperature Drift
V
CM
Output Resistance
V
REF
Output Voltage
V
REF
Output Temperature Drift
V
REF
Output Resistance
V
REF
Line Regulation
–400μA < I
OUT
< 1mA
1.7V < V
DD
< 1.9V
–600μA < I
OUT
< 1mA
I
OUT
= 0
l
The
l
denotes the specifications which apply over the full
operating temperature range, otherwise specifications are at T
A
= 25°C. (Note 5)
CONDITIONS
I
OUT
= 0
l
MIN
0.5
•
V
DD
– 25mV
TYP
0.5
•
V
DD
±25
4
MAX
0.5
•
V
DD
+ 25mV
UNITS
V
ppm/°C
Ω
1.230
1.250
±25
7
0.6
1.270
V
ppm/°C
Ω
mV/V
DIGITAL INPUTS AND OUTPUTS
The
l
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25°C. (Note 5)
PARAMETER
CONDITIONS
SYMBOL
MIN
TYP
MAX
UNITS
ENCODE INPUTS (ENC
+
, ENC
–
)
Differential Encode Mode (ENC
–
Not Tied to GND)
V
ID
V
ICM
V
IN
R
IN
C
IN
Differential Input Voltage
Common Mode Input Voltage
Input Voltage Range
Input Resistance
Input Capacitance
(Note 8)
Internally Set
Externally Set (Note 8)
ENC
+
, ENC
–
to GND (Note 8)
See Figure 10
(Note 8)
l
l
l
0.2
1.2
1.1
0.2
10
3.5
1.6
3.6
V
V
V
V
kΩ
pF
2271f
4
LTC2271
DIGITAL INPUTS AND OUTPUTS
The
l
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25°C. (Note 5)
PARAMETER
High Level Input Voltage
Low Level Input Voltage
Input Voltage Range
Input Resistance
Input Capacitance
High Level Input Voltage
Low Level Input Voltage
Input Current
Input Capacitance
Logic Low Output Resistance to GND
Logic High Output Leakage Current
Output Capacitance
Differential Output Voltage
Common Mode Output Voltage
On-Chip Termination Resistance
CONDITIONS
V
DD
=1.8V
V
DD
=1.8V
ENC
+
to GND
See Figure 11
(Note 8)
V
DD
=1.8V
V
DD
=1.8V
V
IN
= 0V to 3.6V
(Note 8)
V
DD
=1.8V, SDO = 0V
SDO = 0V to 3.6V
(Note 8)
100Ω Differential Load, 3.5mA Mode
100Ω Differential Load, 1.75mA Mode
100Ω Differential Load, 3.5mA Mode
100Ω Differential Load, 1.75mA Mode
Termination Enabled, OV
DD
= 1.8V
l
l
l
l
l
l
l
l
l
l
l
SYMBOL
V
IH
V
IL
V
IN
R
IN
C
IN
V
IH
V
IL
I
IN
C
IN
R
OL
I
OH
C
OUT
V
OD
V
OS
R
TERM
MIN
1.2
TYP
MAX
UNITS
V
Single-Ended Encode Mode (ENC
–
Tied to GND)
0.6
0
30
3.5
1.3
0.6
–10
3
200
–10
3
247
125
1.125
1.125
350
175
1.250
1.250
100
454
250
1.375
1.375
10
10
3.6
V
V
kΩ
pF
V
V
μA
pF
Ω
μA
pF
mV
mV
V
V
Ω
DIGITAL INPUTS (CS, SDI, SCK in Serial or Parallel Programming Mode. SDO in Parallel Programming Mode)
SDO OUTPUT (Serial Programming Mode. Open-Drain Output. Requires 2k Pull-Up Resistor if SDO is Used)
DIGITAL DATA OUTPUTS
POWER REQUIREMENTS
The
l
denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at T
A
= 25°C. (Note 9)
PARAMETER
Analog Supply Voltage
Output Supply Voltage
Analog Supply Current
Digital Supply Current
(Note 10)
(Note 10)
Sine Wave Input
1-Lane Mode, 1.75mA Mode
1-Lane Mode, 3.5mA Mode
2-Lane Mode, 1.75mA Mode
2-Lane Mode, 3.5mA Mode
4-Lane Mode, 1.75mA Mode
4-Lane Mode, 3.5mA Mode
1-Lane Mode, 1.75mA Mode
1-Lane Mode, 3.5mA Mode
2-Lane Mode, 1.75mA Mode
2-Lane Mode, 3.5mA Mode
4-Lane Mode, 1.75mA Mode
4-Lane Mode, 3.5mA Mode
SYMBOL
V
DD
OV
DD
I
VDD
I
OVDD
CONDITIONS
l
l
l
l
l
l
l
l
l
l
l
l
l
l
l
MIN
1.7
1.7
TYP
1.8
1.8
93.3
9.4
17.5
13.4
25.5
21.9
42
185
199
192
214
207
244
1
50
20
MAX
1.9
1.9
103
10.7
19.6
15.5
29
25
47
205
221
214
238
231
270
UNITS
V
V
mA
mA
mA
mA
mA
mA
mA
mW
mW
mW
mW
mW
mW
mW
mW
mW
P
DISS
Power Dissipation
P
SLEEP
P
NAP
P
DIFFCLK
Sleep Mode Power
Nap Mode Power
Power Increase with Diffential Encode Mode Enabled
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