LTC6952IUKG#PBF datasheet, PDF

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LTC6952IUKG#PBF: DescriptionClock Generator 1MHz to 500MHz-IN 4500MHz-OUT 52-Pin QFN EP Tube; File Size6MB，80 Pages; ManufacturerADI; Websitehttps://www.analog.com

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LTC6952IUKG#PBF Overview

Clock Generator 1MHz to 500MHz-IN 4500MHz-OUT 52-Pin QFN EP Tube

LTC6952IUKG#PBF Parametric

Parameter Name	Attribute value
EU restricts the use of certain hazardous substances	Compliant
ECCN (US)	EAR99
Part Status	Active
HTS	8542.39.00.01
Number of Outputs per Chip	11
Clock Input Frequency (MHz)	1 to 500
Maximum Output Frequency (MHz)	4500
Typical Duty Cycle (%)	50
Output Logic Level	CML
Minimum Operating Supply Voltage (V)	3.15
Typical Operating Supply Voltage (V)	3.3
Maximum Operating Supply Voltage (V)	3.45
Minimum Operating Temperature (°C)	-40
Maximum Operating Temperature (°C)	125
Packaging	Tube
Maximum Supply Current (mA)	200
Supplier Package	QFN EP
Pin Count	52
Mounting	Surface Mount
Package Height	0.75(Max)
Package Length	8
Package Width	7
PCB changed	52
Lead Shape	No Lead

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LTC6952

Ultralow Jitter, 4.5GHz PLL

with 11 Outputs and JESD204B/JESD204C Support

FEATURES

DESCRIPTION

The

LTC

6952

is a high performance, ultralow jitter,

JESD204B/C clock generation and distribution IC. It

includes a Phase Locked Loop (PLL) core, consisting of

a reference divider, phase-frequency detector (PFD) with

a phase-lock indicator, ultralow noise charge pump and

integer feedback divider. The LTC6952’s eleven outputs

can be configured as up to five JESD204B/C subclass

1 device clock/SYSREF pairs plus one general purpose

output, or simply eleven general purpose clock outputs for

non-JESD204B/C applications. Each output has its own

individually programmable frequency divider and output

driver. All outputs can also be synchronized and set to

precise phase alignment using individual coarse half-cycle

digital delays and fine analog time delays.

For applications requiring more than eleven total outputs,

multiple LTC6952s can be connected together using the

EZSync or ParallelSync synchronization protocols.

All registered trademarks and trademarks are the property of their respective owners. Protected

by U.S. Patents, including 8319551 and 8819472.

JESD204B/C, Subclass 1 SYSREF Signal Generation

Low Noise Integer-N PLL

Additive Output Jitter < 6fs

RMS

(Integration BW = 12kHz to 20MHz, f = 4.5GHz)

Additive Output Jitter 65fs

RMS

(ADC SNR Method)

EZSync™, ParallelSync™ Multichip Synchronization

–229dBc/Hz Normalized In-Band Phase Noise Floor

–281dBc/Hz Normalized In-Band 1/f Noise

Eleven Independent, Low Noise Outputs with

Programmable Coarse Digital and Fine Analog Delays

Flexible Outputs Can Serve as Either a Device Clock

or SYSREF Signal

Reference Input Frequency up to 500MHz

LTC6952Wizard™ Software Design Tool Support

–40ºC to 125°C Operating Junction Temperature Range

APPLICATIONS

High Performance Data Converter Clocking

Wireless Infrastructure

Test and Measurement

TYPICAL APPLICATION

3.3V

LTC6952Wizard REGISTER VALUES:

FILE: LTC6952 EZSync STANDALONE

48.7

33nF

48.7

1.2µF

0.1µF

Crystek

CVCO55CC-

4000-4000

Vtune

1µF

100

49.9

1µF

REF

–

EZS_SRQ

TO SYNC OUTPUTS:

TOGGLE SSYNC REGISTER BIT

EZS_SRQ

–

OUTx

100

OUTx

–

0.1µF

OUTPUT TERMINATION DETAIL

6952 TA01a

VCO+

REF+

D+

OUT+

22nF

CP+

OUT0

12.5MHz ADC SYSREF

OUT1

500MHz ADC CLOCK

PHASE NOISE (dBc/Hz)

OUT2

12.5MHz ADC SYSREF

OUT3

500MHz ADC CLOCK

OUT4

12.5MHz FPGA SYSREF

OUT5

125MHz FPGA CLOCK

OUT6

100MHz FPGA MGMT CLOCK

VCO

–

VCO

OUT7

12.5MHz DAC SYSREF

OUT8

4GHz DAC CLOCK

OUT9

12.5MHz DAC SYSREF

OUT10

4GHz DAC CLOCK

0.1µF

–100

–110

–120

–130

–140

–150

–160

–170

LTC6952 Phase Noise

RMS JITTER = 65fs

EQUIVALENT ADC SNR METHOD

NOTES 10, 13

0.47µF

LTC6952

0.1µF

4GHz

500MHz

10k

100k

OFFSET FREQUENCY (Hz)

10M 40M

6952 TA01b

Pascal OCXO-E

100MHz Ref Osc

Rev 0

Document Feedback

For more information

www.analog.com

LTC6952

TABLE OF CONTENTS

Features ............................................................................................................................ 1

Applications ....................................................................................................................... 1

Typical Application ............................................................................................................... 1

Description......................................................................................................................... 1

Absolute Maximum Ratings ..................................................................................................... 4

Order Information ................................................................................................................. 4

Pin Configuration ................................................................................................................. 4

Electrical Characteristics ........................................................................................................ 5

Typical Performance Characteristics .......................................................................................... 9

Pin Functions .....................................................................................................................13

Block Diagram....................................................................................................................15

Timing Diagrams ................................................................................................................16

Operation..........................................................................................................................17

Reference Input Buffer .......................................................................................................................................... 17

Reference Divider (R) ........................................................................................................................................... 18

Phase/Frequency Detector (PFD) .......................................................................................................................... 18

Lock Indicator ....................................................................................................................................................... 18

Charge Pump ........................................................................................................................................................ 19

Reference Aligned Output (RAO) Mode ................................................................................................................ 20

VCO Input Buffer................................................................................................................................................... 20

VCO Divider (N) .................................................................................................................................................... 21

Output Dividers (M0 to M10) ................................................................................................................................ 21

Digital Output Delays (DDEL0 to DDEL10) ............................................................................................................ 21

Analog Output Delays (ADEL0 to ADEL10) ........................................................................................................... 21

CML Output Buffers (OUT0 to OUT10) ................................................................................................................. 22

Output Synchronization and SYSREF Generation.................................................................................................. 22

Serial Port ............................................................................................................................................................. 30

Block Power-Down Control ................................................................................................................................... 36

Applications Information .......................................................................................................37

Introduction .......................................................................................................................................................... 37

Output Frequency ................................................................................................................................................. 37

Loop Filter Design ................................................................................................................................................. 37

Digital and Analog Output Delays.......................................................................................................................... 38

Reference Input .................................................................................................................................................... 38

VCO Input ............................................................................................................................................................. 38

EZS_SRQ Input ..................................................................................................................................................... 41

JESD204B/C Design Example Using EZSync Standalone ...................................................................................... 41

JESD204B/C Design Example Using Ezsync Multi-Chip ........................................................................................ 48

Reference Source Considerations ......................................................................................................................... 64

In-Band Output Phase Noise ................................................................................................................................. 65

Output Phase Noise Due To 1/f Noise ................................................................................................................... 65

Reference Signal Routing, Spurious, and Phase Noise ......................................................................................... 65

Supply Bypassing and PCB Layout Guidelines ...................................................................................................... 66

Rev 0

For more information

www.analog.com

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