EEWORLDEEWORLDEEWORLD

Part Number

Search

54111-413-30-1700LF

Description
Board Connector, 30 Contact(s), 1 Row(s), Male, Straight, 0.1 inch Pitch, Solder Terminal, Locking, Black Insulator, Receptacle
CategoryThe connector    The connector   
File Size63KB,1 Pages
ManufacturerAmphenol
Websitehttp://www.amphenol.com/
Environmental Compliance
Download Datasheet Parametric View All

54111-413-30-1700LF Overview

Board Connector, 30 Contact(s), 1 Row(s), Male, Straight, 0.1 inch Pitch, Solder Terminal, Locking, Black Insulator, Receptacle

54111-413-30-1700LF Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerAmphenol
Reach Compliance Codecompliant
ECCN codeEAR99
body width0.094 inch
subject depth0.669 inch
body length3 inch
Body/casing typeRECEPTACLE
Connector typeBOARD CONNECTOR
Contact to complete cooperationSN ON NI
Contact completed and terminatedMatte Tin (Sn) - with Nickel (Ni) barrier
Contact point genderMALE
Contact materialPHOSPHOR BRONZE
contact modeRECTANGULAR
Contact styleSQ PIN-SKT
Insulation resistance5000000000 Ω
Insulator colorBLACK
insulator materialTHERMOPLASTIC
JESD-609 codee3
Manufacturer's serial number54111
Plug contact pitch0.1 inch
Installation option 1LOCKING
Installation methodSTRAIGHT
Installation typeBOARD
Number of connectorsONE
PCB row number1
Number of rows loaded1
Maximum operating temperature125 °C
Minimum operating temperature-65 °C
PCB contact patternRECTANGULAR
Plating thickness30u inch
Rated current (signal)3 A
GuidelineUL, CSA
reliabilityCOMMERCIAL
Terminal length0.095 inch
Terminal pitch2.54 mm
Termination typeSOLDER
Total number of contacts30
PDM: Rev:E
STATUS:
Released
Printed: Jun 03, 2008
.
Quartus2 simulation can not produce waveform
I use quaratus2 to do waveform simulation. There is no problem with compilation and code, but the waveform cannot be simulated. It prompts the error code: Error: (vsim_3170) Could not find 'work.PPQ_v...
Mr.Sensitive FPGA/CPLD
[Xiao Meige FPGA Advanced Tutorial] Chapter 11 Four-channel Amplitude-Frequency-Phase Adjustable DDS Signal Generator Part 2
[b]Custom frame of signal generator[/b] [color=#000][size=15px]From the previous experimental purpose, we know that we need to use the serial port to control the parameters of the waveform. Generally ...
芯航线跑堂 FPGA/CPLD
How do you analyze the DC blocking function of capacitors?
If a large capacitor is connected in series after an AC input, the output on the other leg of the capacitor will be the same as the AC input.If a large capacitor is connected in series after a DC inpu...
mamagoose Analog electronics
After the microcontroller is connected to the computer via a USB cable, the problem of "unrecognized USB device" appears
After the microcontroller is connected to the computer via a USB cable, the problem of "unrecognizable USB device" appears. I wanted to imitate Atom's one-click download circuit and make a minimum sys...
反倒是fdsf stm32/stm8
Logic Levels Explained
Detailed explanation of logic level 1. TTL level (what is TTL level): Output high level>2.4V, output low level=2.0V, input low levelcmos 3.3v), level conversion is required when connecting to each oth...
liuyong1989 Power technology
I saw the posts about “competition” today and it’s really embarrassing!
I saw the posts about “competition” today and it’s really embarrassing!...
蓝雨夜 Talking

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 1559  2495  296  78  2287  32  51  6  2  47 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号