ABSOLUTE MAXIMUM RATINGS
V
CC
to Common Ground .............................................. 0V to +16.5V
V
LOGIC
to Common Ground ............................................... 0V to +7V
Analog Common to Digital Common Ground ............... -0.5V to +1V
Digital Inputs to Common Ground .................... -0.5V to V
LOGIC
+0.5V
Digital Outputs to Common Ground ................. -0.5V to V
LOGIC
+0.5V
Multiplexer Analog Inputs ...................................... -16.5V to +31.5V
Gain and Offset Adjustment ................................ -0.5V to V
CC
+0.5V
Analog Input Maximum Current ........................................... 100mA
Temperature with Bias Applied ............................. -55°C to +125°C
Storage Temperature ............................................ -65°C to +150°C
Lead Temperature, Soldering .................................... 300°C, 10sec
CAUTION:
ESD (ElectroStatic Discharge) sensitive
device. Permanent damage may occur on
unconnected devices subject to high energy
electrostatic fields. Unused devices must be
stored in conductive foam or shunts.
Personnel should be properly grounded prior
to handling this device. The protective foam
should be discharged to the destination
socket before devices are removed.
SPECIFICATIONS
(T
A
= 25°C and nominal supply voltages unless otherwise noted)
MIN.
ANALOG INPUTS
Input Voltage Range
Multiplexer Inputs
Configuration
Input Impedance
ON Channel
OFF Channel
Input Bias Current/Channel
Crosstalk
OFF to ON Channel
TYP.
0 to +5
MAX.
UNIT
V
CONDITIONS
8
Single-ended
10
9
10
10
+10
+250
-90
-80
-70
Ω
Ω
nA
nA
dB
dB
dB
Bits
LSB
LSB
LSB
LSB
LSB
%FSR
Parallel with 30pF
Parallel with 5pF
25°C
-55°C to +125°C
10kHz, 0V to +5V
Pk-to-pk
50kHz, 0V to +5V
Pk-to-pk
100kHz, 0V to +5V
Pk-to-pk
ACCURACY
Resolution
12
Linearity Error
–K
+0.5
–J
+1
Differential Non-Linearity
–K
+1
–J
+2
Offset Error
+0.5
+4
Gain Error
+0.3
+1
No Missing Codes
–K
Guaranteed
TRANSFER CHARACTERISTICS
Throughput Rate
100
MUX Settling/Acquisition
1.9
A/D Conversion
8.1
STABILITY
+0.5
+2.5
Linearity
Offset
+5
+25
Gain
+10
+50
DIGITAL INPUTS
Capacitance
5
Logic Levels
V
IH
+2.4
+5.5
V
IL
-0.5
+0.8
I
IH
+5
I
IL
+5
Adjustable to zero
Adjustable to zero
kHz
µs
µs
ppm/°C
ppm/°C
ppm/°C
pF
V
V
µA
µA
SP8121DS/02
SP8121 Monolithic, 12-Bit Data Acquisition System
© Copyright 2000 Sipex Corporation
2
SP8121 PINOUT
DB11 (MSB)
SP8121 CONTROL TRUTH TABLE
CE
DB0 (LSB)
LATCH
R/C
0
0
H ->L
1
OPERATION
Start Conversion
Start Conversion
Start Conversion
Enable 12-bit Output
(when STATUS=0)
L->H
1
1
S
DB10
MA2
MA1
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
MA0
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
CLOCK
REF
12-BIT ADC
DECODE
8-CHANNEL
MULTIPLEXER
5
6
7
8
9 10 11 12 13 14 15 16
1
CONTROL
LOGIC
1
2
3
4
SP8121 MULTIPLEXER TRUTH TABLE
LATCH MA
2
H -> L
H -> L
H -> L
H -> L
H -> L
0
0
0
0
1
1
1
1
X
X
MA
1
0
0
1
1
0
0
1
1
X
X
MA
0
0
1
0
1
0
1
0
1
X
X
OPERATION
CH
O
Selected
CH
1
Selected
CH
2
Selected
CH
3
Selected
CH
4
Selected
CH
5
Selected
CH
6
Selected
CH
7
Selected
Prev. CH “n” Held
Prev. CH “n” Held
OFFSET ADJ.
ANA. IN. CH0
ANA. IN. CH1
ANA. IN. CH2
ANA. IN. CH3
ANA. IN. CH4
ANA. IN. CH5
ANA. IN. CH6
SP8121 PINOUT
STATUS — Identifies valid data output; goes to
logic high during conversion; goes to logic low
when conversion is completed and data is valid
R/C — Read/Convert — Initiates conversion on
the high-to-low transition; logic low discon-
nects data bus; logic high initiates read
CE — Chip Enable — Logic low disables read
or convert; logic high enables read or convert
LATCH — MUX Address Latch — Logic high
to low transition captures MUX address on
MUX address lines
MA
0
, MA
1
, MA
2
— MUX Address 0, 1 & 2 —
Selects analog input channels CH
0
through CH
7
DB
0
through DB
11
— Data Outputs — Logic
high is binary true; logic low binary false
ANA. IN. CH7
GAIN ADJ.
ANA. GND.
STATUS
CE
V
LOGIC
V
CC
R/C
H -> L
H -> L
H -> L
0
1
SP8121DS/02
SP8121 Monolithic, 12-Bit Data Acquisition System
© Copyright 2000 Sipex Corporation
4
FEATURES
The
SP8121
is a complete data acquisition systems,
featuring 8-channel multiplexer, internal reference
and 12-bit sampling A/D converter implemented as a
single monolithic IC. The analog multiplexer accepts
0V to +5V unipolar full scale inputs. Output data is
formatted in 12-bit parallel.
Linearity errors of +0.5 and +1.0 LSB, and Differen-
tial Non-linearity to 12-bits is guaranteed, with no
missing codes over temperature. Channel-to-channel
crosstalk is typically -85dB. Multiplexer settling plus
acquisition time is 1.9µs maximum; A/D conversion
time is 8.1µs maximum.
The
SP8121
is available in a 32-pin plastic DIP or
SOIC packages. Operating temperature range is 0°C
to +70°C commercial.
The SAR, timed by the clock, sequences through the
conversion cycle and returns an end–of–convert flag
to the control section of the ADC. The clock is then
disabled by the control section, which puts the STA-
TUS output line low. The control section is enabled to
allow the data to be read by external command (R/C).
MULTIPLEXER CONTROL
On the
SP8121
the address lines MA0, MA1, and
MA2 are latched into the internal address decode
circuitry with the falling edge of LATCH. Data set-up
time for these inputs is >=50nS. The MUX address
data must remain valid for the current conversion for
a minimum of 3.0
µS
after the conversion is initiated.
This is the time required for the MUX and Sample and
Hold to settle. However it is advisable that the MUX
not be changed at all during the full 10µS conversion
time due to capacitive coupling effects of digital edges
through the silicon.
The
SP8121
multiplexer inputs have been designed to
allow substantial overvoltage conditions to occur
without any damage. The inputs are diode-clamped
and further protected with a 200Ω series resistor. As
a result, momentary (10 seconds) input voltages can
be as low as -16.5V or as high as +31.5V with no
change or degradation in multiplexer performance or
crosstalk. This feature allows the output voltage of an
externally connected op amp to swing to +15V supply
levels with no multiplexer damage. Complicated
power-up sequencing is not required to protect the
SP8121.
The multiplexer inputs may be damaged,
however, if the inputs are allowed to either source or
sink greater than 100mA.
INITIATING A CONVERSION
CIRCUIT OPERATION
The
SP8121
is a complete 8-channel data acquisition
systems (DAS), with on-board multiplexer, voltage
reference, sample-and-hold, clock and tri-state
outputs. The digital control architecture is very similar
to the industry-standard 574-type A/D, and uses
identical control lines and digital states.
The multiplexer for the
SP8121
is identical in
operation to many discrete devices available today,
except that it has been integrated into the single-chip
DAS. The appropriate channel is selected using the
MUX address lines MA
0
, MA
1
, and MA
2
per the truth
table. The selected analog input is fed through to the
ADC. The input impedance into any MUX channel
will be on the order to 10
9
ohms, since it is connected
to the integral sampling structure of the capacitor
DAC. Crosstalk is kept to -85dB at 0V to 5V
p-p
over an
input frequency range of 10kHz to 50kHz.
When the control section of the
SP8121
initiates a
conversion command the internal clock is enabled,
and the successive approximation register (SAR) is
reset to all zeros. Once the conversion has been started
it cannot be stopped or restarted. Data is not available
at the output buffers until the conversion has been
completed.
The
SP8121
was designed to require a minimum of
control to perform a 12-bit conversion. The control
input used are R/C which tri-states the outputs when
high and starts the conversion when low, in combina-
tion with CE. The last of the control inputs to reach the
correct state starts the conversion, therefore either may
be dynamically controlled. The nominal delay from
each is the same and they may change state simulta-
neously. In order to ensure that a particular input
controls the conversion, the other should be set up at
least 50ns earlier. The STATUS line indicates when
a conversion is in process and when it is complete.
SP8121DS/02
SP8121 Monolithic, 12-Bit Data Acquisition System
© Copyright 2000 Sipex Corporation
5
京公网安备 11010802033920号
EEWORLD
