54122-409-25-1150R datasheet, PDF

54122-409-25-1150R: DescriptionBoard Connector, 50 Contact(s), 2 Row(s), Male, Straight, 0.1 inch Pitch, Solder Kinked Leads Terminal, Locking, Black Insulator, Receptacle,; CategoryThe connector The connector; File Size107KB，1 Pages; ManufacturerAmphenol; Websitehttp://www.amphenol.com/

Download Datasheet Parametric View All

54122-409-25-1150R Overview

Board Connector, 50 Contact(s), 2 Row(s), Male, Straight, 0.1 inch Pitch, Solder Kinked Leads Terminal, Locking, Black Insulator, Receptacle,

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Objectid	306122750
Reach Compliance Code	compliant
Country Of Origin	France
ECCN code	EAR99
YTEOL	9.4
body width	0.19 inch
subject depth	0.453 inch
body length	2.5 inch
Body/casing type	RECEPTACLE
Connector type	BOARD CONNECTOR
Contact to complete cooperation	SN ON NI
Contact completed and terminated	Tin/Lead (Sn/Pb) - with Nickel (Ni) barrier
Contact point gender	MALE
Contact material	PHOSPHOR BRONZE
contact mode	RECTANGULAR
Contact style	SQ PIN-SKT
Insulation resistance	5000000000 Ω
Insulator color	BLACK
insulator material	POLYETHYLENE
JESD-609 code	e0
Manufacturer's serial number	54122
Plug contact pitch	0.1 inch
Match contact row spacing	0.1 inch
Installation option 1	LOCKING
Installation method	STRAIGHT
Installation type	BOARD
Number of connectors	ONE
PCB row number	2
Number of rows loaded	2
Maximum operating temperature	125 °C
Minimum operating temperature	-65 °C
PCB contact pattern	RECTANGULAR
PCB contact row spacing	2.54 mm
Plating thickness	79u inch
Rated current (signal)	3 A
Guideline	UL, CSA
reliability	COMMERCIAL
Terminal length	0.12 inch
Terminal pitch	2.54 mm
Termination type	SOLDER KINKED LEADS
Total number of contacts	50

PDM: Rev:K

STATUS:

Released

Printed: Mar 10, 2011

Purgatory Legend-RAM War: Calling and verifying IP core RAM...; 雷北城 FPGA/CPLD

【Altera SoC Experience Tour】High-speed Data Acquisition System Design: [i=s]This post was last edited by chenzhufly on 2015-3-26 00:14[/i] [align=center][size=4][b]Author: chenzhufly QQ[/b][b]: 36886052[/b][/size][/align][align=left][size=4][b]1. Hardware environment[/b]...; chenzhufly FPGA/CPLD

Looking for a Verilog solution?: [color=#FF0000]Timer for competition (with reset button, start/pause button, 4 digital tubes)[/color] Please write it in Verilog language!!!...; jbcfelix Embedded System

Re-understanding of analog ground and digital ground: In order to achieve good anti-interference, we often see ground splitting wiring on PCB boards. However, not all digital circuits and analog circuits must be split on the ground plane. Because this sp...; xiefei FPGA/CPLD

Problems with CRect and RECT: If I assign a CRect object to a RECT object, will there be any problems? For example, if a function parameter is of type RECT, but a CRect object is passed in as a parameter, will there be any problem...; emaster Embedded System

Matrix keyboard: Why when I turn on the switch when scanning the matrix keyboard, it always displays 0, which is the number of the keys in the first row and first column. It should display nothing. I can't figure it o...; Learner_new 51mcu

Shortcut: 00 01 02 03 04 05 06 07 08 09 0A 0C 0F 0J 0L 0M 0R 0S 0T 0Z 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 1H 1K 1M 1N 1P 1S 1T 1V 1X 1Z 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 2G 2K 2M 2N 2P 2Q 2R 2S 2T 2W 2Z 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 3G 3H 3J 3K 3L 3M 3N 3P 3R 3S 3T 3V 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4M 4N 4P 4S 4T 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5E 5G 5H 5K 5M 5N 5P 5S 5T 5V 60 61 62 63 64 65 66 67 68 69 6A 6C 6E 6F 6M 6N 6P 6R 6S 6T 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7M 7N 7P 7Q 7V 7W 7X 80 81 82 83 84 85 86 87 88 89 8A 8D 8E 8L 8N 8P 8S 8T 8W 8Y 8Z 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9F 9G 9H 9L 9S 9T 9W

Popular Components