PMN45EN
TrenchMOS™ enhanced logic level FET
M3D302
Rev. 01 — 27 September 2002
Product data
1. Description
N-channel enhancement mode field-effect transistor in a plastic package using
TrenchMOS™ technology.
Product availability:
PMN45EN in SOT457 (TSOP6).
2. Features
s
s
s
s
TrenchMOS™ technology
Very fast switching
Low threshold voltage
Surface mount package.
3. Applications
s
s
s
s
Battery powered motor control
Load switch in notebook computers
High speed switch in set top box power supplies
Driver FET in DC to DC converters.
4. Pinning information
Table 1:
Pin
1,2,5,6
3
4
Pinning - SOT457 (TSOP6), simplified outline and symbol
Description
drain (d)
gate (g)
source (s)
1
Top view
2
3
MBK092
Simplified outline
6
5
4
Symbol
d
g
s
MBB076
SOT457 (TSOP6)
Philips Semiconductors
PMN45EN
TrenchMOS™ enhanced logic level FET
5. Quick reference data
Table 2:
V
DS
I
D
P
tot
T
j
R
DSon
Quick reference data
Conditions
25
°C ≤
T
j
≤
150
°C
T
sp
= 25
°C;
V
GS
= 10 V
T
sp
= 25
°C
V
GS
= 10 V; I
D
= 3 A; T
j
= 25
°C
V
GS
= 4.5 V; I
D
= 2.8 A; T
j
= 25
°C
Typ
-
-
-
-
32
42
Max
30
5.2
1.75
150
40
50
Unit
V
A
W
°C
mΩ
mΩ
drain-source voltage (DC)
drain current (DC)
total power dissipation
junction temperature
drain-source on-state resistance
Symbol Parameter
6. Limiting values
Table 3: Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
V
DS
V
GS
I
D
I
DM
P
tot
T
stg
T
j
I
S
drain-source voltage (DC)
gate-source voltage (DC)
drain current (DC)
peak drain current
total power dissipation
storage temperature
junction temperature
source (diode forward) current (DC) T
sp
= 25
°C
T
sp
= 25
°C;
V
GS
= 10 V
T
sp
= 70
°C;
V
GS
= 10 V
T
sp
= 25
°C;
pulsed; t
p
≤
10
µs
T
sp
= 25
°C
Conditions
25
°C ≤
T
j
≤
150
°C
Min
-
-
-
-
-
-
−55
−55
-
Max
30
20
5.2
4.2
21.1
1.75
+150
+150
1.45
Unit
V
V
A
A
A
W
°C
°C
A
Source-drain diode
9397 750 10193
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 01 — 27 September 2002
2 of 12
Philips Semiconductors
PMN45EN
TrenchMOS™ enhanced logic level FET
03aa17
120
Pder
(%)
120
I
der
(%)
80
03aa25
80
40
40
0
0
50
100
150
Tsp (°C)
200
0
0
50
100
150
200
Tsp
(°C)
P
tot
P
der
=
----------------------
×
100%
P
°
tot
(
25 C
)
I
D
I
der
=
------------------
×
100%
-
I
°
D
(
25 C
)
Fig 1. Normalized total power dissipation as a
function of solder point temperature.
Fig 2. Normalized continuous drain current as a
function of solder point temperature.
102
ID
(A)
10
Limit RDSon = VDS / ID
tp = 10
µs
100
µs
1 ms
1
DC
10-1
10 ms
100 ms
03aj70
10-2
10-3
10-1
1
10
VDS (V)
102
T
sp
= 25
°C;
I
DM
is single pulse.
Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage.
9397 750 10193
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 01 — 27 September 2002
3 of 12
Philips Semiconductors
PMN45EN
TrenchMOS™ enhanced logic level FET
7. Thermal characteristics
Table 4:
R
th(j-sp)
Thermal characteristics
Conditions
Min Typ Max Unit
-
70
K/W
thermal resistance from junction to solder point mounted on a metal clad board;
Figure 4
-
Symbol Parameter
7.1 Transient thermal impedance
102
03aj69
Zth(j-sp)
(K/W)
δ
= 0.5
0.2
10
0.1
0.05
0.02
single pulse
1
10-4
10-3
10-2
10-1
1
10
tp (s)
102
Fig 4. Transient thermal impedance from junction to solder point as a function of pulse duration.
9397 750 10193
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 01 — 27 September 2002
4 of 12
Philips Semiconductors
PMN45EN
TrenchMOS™ enhanced logic level FET
8. Characteristics
Table 5: Characteristics
T
j
= 25
°
C unless otherwise specified.
Symbol Parameter
Static characteristics
V
(BR)DSS
drain-source breakdown voltage
V
GS(th)
I
DSS
I
GSS
R
DSon
gate-source threshold voltage
drain-source leakage current
gate-source leakage current
drain-source on-state resistance
I
D
= 250
µA;
V
GS
= 0 V
I
D
= 1 mA; V
DS
= V
GS
V
DS
= 30 V; V
GS
= 0 V
V
GS
=
±20
V; V
DS
= 0 V
V
GS
= 10 V; I
D
= 3 A;
Figure 7
and
8
V
GS
= 4.5 V; I
D
= 2.8 A;
Figure 7
and
8
Dynamic characteristics
Q
g(tot)
Q
gs
Q
gd
C
iss
C
oss
C
rss
t
d(on)
t
r
t
d(off)
t
f
V
SD
total gate charge
gate-source charge
gate-drain (Miller) charge
input capacitance
output capacitance
reverse transfer capacitance
turn-on delay time
rise time
turn-off delay time
fall time
source-drain (diode forward) voltage I
S
= 1.7 A; V
GS
= 0 V;
Figure 12
V
DD
= 15 V; R
D
= 12
Ω;
V
GS
= 4.5 V; R
G
= 6
Ω
V
GS
= 0 V; V
DS
= 25 V; f = 1 MHz;
Figure 11
V
DD
= 15 V; V
GS
= 4.5 V; I
D
= 5 A;
Figure 13
-
-
-
-
-
-
-
-
-
-
-
6.1
1.7
2.35
495
100
70
14
19
28
16
0.75
-
-
-
-
-
-
-
-
-
-
1.2
nC
nC
nC
pF
pF
pF
ns
ns
ns
ns
V
30
1
-
-
-
-
-
1.5
0.01
10
32
42
-
2
1.0
100
40
50
V
V
µA
nA
mΩ
mΩ
Conditions
Min
Typ
Max
Unit
Source-drain diode
9397 750 10193
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 01 — 27 September 2002
5 of 12
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