PCA24S08A
1024
×
8-bit CMOS EEPROM with access protection
Rev. 01 — 19 January 2010
Product data sheet
1. General description
The PCA24S08A provides 8192 bits of serial Electrically Erasable and Programmable
Read-Only Memory (EEPROM) organized as 1024 words of 8 bits each. Data bytes are
received and transmitted via the serial I
2
C-bus.
Access permissions limiting reads or writes are set via the I
2
C-bus to isolate blocks of
memory from improper access.
The PCA24S08A is intended to be pin compatible with standard 24C08 serial EEPROM
devices except for pins 1, 2, and 3, which are address pins in the standard part. Other
exceptions to the PCA24S08A serial EEPROM data sheet are noted in
Section 6.6.
All bits are sent to or read from the device, most significant bit first, in a manner consistent
with the 24C08 serial EEPROM. The bit fields in this document are correspondingly listed
with the MSB on the left and the LSB on the right.
The EEPROM memory is broken up into 8 blocks of 1 kbit (128 bytes) each. Within each
block, the memory is physically organized in to 8 pages of 128 bits (16 bytes) each. In
addition to these 8 kbits, there are two more 128-bit pages that are used to store the
access protection and ID information. There are a total of 8448 bits of EEPROM memory
available in the PCA24S08A.
Access protection (both read and write) is organized on a block basis for block 1 through
block 7 and on a page and a block basis for block 0. Protection information for these
blocks and pages is stored in one of the additional pages of EEPROM memory that is
addressed separately from the main data storage array. SeeSection
6.4
for more details.
The ID value is located in the ID page of the EEPROM, the second of the additional
16 byte pages.
Writes from the serial interface may include from one byte to 16 bytes at a time,
depending on the protocol followed by the bus master. All page accesses must be
properly aligned to the internal EEPROM page.
The EEPROM memory offers an endurance of 100,000 write cycles per byte, with 10 year
data retention. Writes to the EEPROM take less than 5 ms to complete.
After manufacturing, all EEPROM bits will be set to a value of ‘1’.
NXP Semiconductors
PCA24S08A
1024
×
8-bit CMOS EEPROM with access protection
2. Features
Non-volatile storage of 8 kbits organized as 8 blocks of 128 bytes each
I
2
C-bus interface logic
Compatible with 24C08 serial EEPROM, and alternate source of Atmel AT24RF08C
without the RF interface
Write operation:
Byte write mode
16-byte page write mode
Read operation:
Sequential read
Random read
Programmable access protection to limit reads and writes
Lock/unlock function
Write protect feature protecting the full memory array against write operations
Self timed write cycle
Internal power-on reset
High reliability:
Ten years non-volatile data retention time
100,000 write cycle endurance
Low power CMOS technology
Operating power supply voltage range of 2.5 V to 3.6 V
0 Hz to 400 kHz clock frequency
ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per
JESD22-A115 and 1000 V CDM per JESD22-C101
Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
Packages offered: SO8, TSSOP8
3. Ordering information
Table 1.
Ordering information
T
amb
=
−
40
°
C to +85
°
C
Type number
PCA24S08AD
PCA24S08ADP
Topside
mark
P24S08A
PS08A
Package
Name
SO8
TSSOP8
Description
plastic small outline package; 8 leads; body width 3.9 mm
plastic thin shrink small outline package; 8 leads; body width 3 mm
Version
SOT96-1
SOT505-1
PCA24S08A_1
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 01 — 19 January 2010
2 of 24
NXP Semiconductors
PCA24S08A
1024
×
8-bit CMOS EEPROM with access protection
4. Block diagram
PCA24S08A
SDA
SCL
INPUT
FILTER
I
2
C-BUS CONTROL LOGIC
WP
PROT
BYTE
COUNTER
EEPROM
8 PAGES
(8
×
128 BYTES EACH)
ACCESS
PROTECTION
SEQUENCER
DIVIDER
(÷ 128)
BYTE LATCH
(8 BYTES)
ADDRESS
POINTER
IDENTIFICATION
NUMBER
EE
CONTROL
V
DD
POWER-ON RESET
TIMER
(÷ 16)
OSCILLATOR
002aae786
V
SS
Fig 1.
Block diagram
5. Pinning information
5.1 Pinning
n.c.
n.c.
PROT
V
SS
1
2
8
7
V
DD
WP
SCL
SDA
n.c.
n.c.
PROT
V
SS
1
2
3
4
002aae785
8
7
V
DD
WP
SCL
SDA
PCA24S08AD
3
4
002aae784
6
5
PCA24S08ADP
6
5
Fig 2.
Pin configuration for SO8
Fig 3.
Pin configuration for TSSOP8
PCA24S08A_1
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 01 — 19 January 2010
3 of 24
NXP Semiconductors
PCA24S08A
1024
×
8-bit CMOS EEPROM with access protection
5.2 Pin description
Table 2.
Symbol
n.c.
PROT
V
SS
SDA
SCL
WP
V
DD
Pin description
Pin
1, 2
3
4
5
6
7
8
Description
not connected
active LOW protect reset input
ground supply voltage
serial data; open-drain I/O
serial clock; open-drain input
active HIGH write protect input
supply voltage
6. Functional description
Refer to
Figure 1 “Block diagram”.
6.1 Device addressing
Following a START condition, the bus master must output the address of the slave it is
accessing. The address of the PCA24S08A is shown in
Figure 4.
1
0
1
fixed
0
1
B2
B1 R/W
sofware
selectable
002aae789
Fig 4.
Slave address
The last bit of the slave address defines the operation to be performed. When set to
logic 1 a read operation is selected, while logic 0 selects a write operation. Bits B2 and B1
in the slave address represent the 2 most significant bits of the word to be addressed. The
third device address bit in the I
2
C-bus protocol that is usually matched to A2 (pin 3) on a
standard 24C08 serial EEPROM is internally connected HIGH, so device addresses A8h
through AFh (hex) are used to access the memory on the chip.
6.2 Write operations
Write operations on the device can be performed only when WP is held LOW. When the
WP pin is held HIGH, content of the full memory is protected (Block 0 to Block 7,
APP registers, ID Page), and no write operation is allowed.
6.2.1 Byte/word write
Write command may be used to set the address for a subsequent Read command. For a
write operation, the PCA24S08A requires a second address field. The address field
associated with the two software selectable bits in the slave address is a word address
providing access to the 1024 bytes of memory, as shown in
Figure 5.
Upon receipt of the
word address, the PCA24S08A responds with an acknowledge and awaits the next 8 bits
of data, again responding with an acknowledge. Word address is automatically
incremented.
PCA24S08A_1
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 01 — 19 January 2010
4 of 24
NXP Semiconductors
PCA24S08A
1024
×
8-bit CMOS EEPROM with access protection
BYTE 0
0
PAGE 0
0
0
0
BYTE 15
BLOCK 0
0
0
0
BYTE 0
0
PAGE 7
1
1
1
BYTE 15
1
1
1
1
0
0
0
1
1
1
1
0
0
0
BYTE 0
0
PAGE 0
0
0
0
BYTE 15
BLOCK 7
1
1
1
BYTE 0
0
PAGE 7
1
1
1
BYTE 15
1
1
1
1
0
0
0
1
1
1
1
0
0
0
1
0
1
fixed
0
1
B2
B1 R/W
B0
P2
P1
page
number
P0
A3
A2
A1
A0
block number
byte
address
002aae790
Fig 5.
Memory addressing
Figure 6
shows how the memory array is addressed when the slave address byte and
address field byte are sent. The master terminates the transfer by generating a STOP
condition. After this STOP condition, the Erase/Write (E/W) cycle starts and the I
2
C-bus is
free for another transmission. Up to 16 bytes of data can be written in the slave writing
sequence (E/W cycle).
PCA24S08A_1
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 01 — 19 January 2010
5 of 24
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