PCA9548A
8-channel I
2
C-bus switch with reset
Rev. 03 — 7 July 2009
Product data sheet
1. General description
The PCA9548A is an octal bidirectional translating switch controlled via the I
2
C-bus. The
SCL/SDA upstream pair fans out to eight downstream pairs, or channels. Any individual
SCx/SDx channel or combination of channels can be selected, determined by the
contents of the programmable control register.
An active LOW reset input allows the PCA9548A to recover from a situation where one of
the downstream I
2
C-buses is stuck in a LOW state. Pulling the RESET pin LOW resets the
I
2
C-bus state machine and causes all the channels to be deselected as does the internal
Power-on reset function.
The pass gates of the switches are constructed such that the V
DD
pin can be used to limit
the maximum high voltage which will be passed by the PCA9548A. This allows the use of
different bus voltages on each pair, so that 1.8 V or 2.5 V or 3.3 V parts can communicate
with 5 V parts without any additional protection. External pull-up resistors pull the bus up
to the desired voltage level for each channel. All I/O pins are 5 V tolerant.
2. Features
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
1-of-8 bidirectional translating switches
I
2
C-bus interface logic; compatible with SMBus standards
Active LOW reset input
3 address pins allowing up to 8 devices on the I
2
C-bus
Channel selection via I
2
C-bus, in any combination
Power-up with all switch channels deselected
Low R
on
switches
Allows voltage level translation between 1.8 V, 2.5 V, 3.3 V and 5 V buses
No glitch on power-up
Supports hot insertion
Low standby current
Operating power supply voltage range of 2.3 V to 5.5 V
5 V tolerant inputs
0 Hz to 400 kHz clock frequency
ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per
JESD22-A115, and 1000 V CDM per JESD22-C101
I
Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
I
Three packages offered: SO24, TSSOP24, and HVQFN24
NXP Semiconductors
PCA9548A
8-channel I
2
C-bus switch with reset
3. Ordering information
Table 1.
Ordering information
Package
Name
PCA9548ABS
PCA9548AD
PCA9548APW
HVQFN24
SO24
TSSOP24
Description
Version
plastic thermal enhanced very thin quad flat package; SOT616-1
no leads; 24 terminals; body 4
×
4
×
0.85 mm
plastic small outline package; 24 leads;
body width 7.5 mm
plastic thin shrink small outline package; 24 leads;
body width 4.4 mm
SOT137-1
SOT355-1
Type number
3.1 Ordering options
Table 2.
Ordering options
Topside mark
548A
PCA9548AD
PCA9548A
Temperature range
−40 °C
to +85
°C
−40 °C
to +85
°C
−40 °C
to +85
°C
Type number
PCA9548ABS
PCA9548AD
PCA9548APW
PCA9548A_3
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 7 July 2009
2 of 26
NXP Semiconductors
PCA9548A
8-channel I
2
C-bus switch with reset
5.2 Pin description
Table 3.
Symbol
A0
A1
RESET
SD0
SC0
SD1
SC1
SD2
SC2
SD3
SC3
V
SS
SD4
SC4
SD5
SC5
SD6
SC6
SD7
SC7
A2
SCL
SDA
V
DD
[1]
Pin description
Pin
SO24, TSSOP24
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
HVQFN24
22
23
24
1
2
3
4
5
6
7
8
9
[1]
10
11
12
13
14
15
16
17
18
19
20
21
address input 0
address input 1
active LOW reset input
serial data 0
serial clock 0
serial data 1
serial clock 1
serial data 2
serial clock 2
serial data 3
serial clock 3
supply ground
serial data 4
serial clock 4
serial data 5
serial clock 5
serial data 6
serial clock 6
serial data 7
serial clock 7
address input 2
serial clock line
serial data line
supply voltage
Description
HVQFN24 package die supply ground is connected to both the V
SS
pin and the exposed center pad. The
V
SS
pin must be connected to supply ground for proper device operation. For enhanced thermal, electrical,
and board-level performance, the exposed pad needs to be soldered to the board using a corresponding
thermal pad on the board, and for proper heat conduction through the board thermal vias need to be
incorporated in the PCB in the thermal pad region.
PCA9548A_3
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 7 July 2009
5 of 26
FPGA/CPLD
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