PCA9553
4-bit I
2
C-bus LED driver with programmable blink rates
Rev. 06 — 29 December 2008
Product data sheet
1. General description
The PCA9553 LED blinker blinks LEDs in I
2
C-bus and SMBus applications where it is
necessary to limit bus traffic or free up the I
2
C-bus master's (MCU, MPU, DSP, chip set,
etc.) timer. The uniqueness of this device is the internal oscillator with two programmable
blink rates. To blink LEDs using normal I/O expanders like the PCF8574 or PCA9554, the
bus master must send repeated commands to turn the LED on and off. This greatly
increases the amount of traffic on the I
2
C-bus and uses up one of the master's timers. The
PCA9553 LED blinker instead requires only the initial set-up command to program
BLINK RATE 1 and BLINK RATE 2 (i.e., the frequency and duty cycle). From then on, only
one command from the bus master is required to turn each individual open-drain output
ON, OFF, or to cycle at BLINK RATE 1 or BLINK RATE 2. Maximum output sink current is
25 mA per bit and 100 mA per package.
Any bits not used for controlling the LEDs can be used for General Purpose Parallel
Input/Output (GPIO) expansion.
Power-On Reset (POR) initializes the registers to their default state, all zeroes, causing
the bits to be set HIGH (LED off).
Due to pin limitations, the PCA9553 is not featured with hardware address pins. The
PCA9553/01 and the PCA9553/02 have different fixed I
2
C-bus addresses allowing
operation of both on the same bus.
2. Features
I
4 LED drivers (on, off, flashing at a programmable rate)
I
2 selectable, fully programmable blink rates (frequency and duty cycle) between
0.172 Hz and 44 Hz (5.82 seconds and 0.023 seconds)
I
Input/outputs not used as LED drivers can be used as regular GPIOs
I
Internal oscillator requires no external components
I
I
2
C-bus interface logic compatible with SMBus
I
Internal power-on reset
I
Noise filter on SCL/SDA inputs
I
4 open-drain outputs directly drive LEDs to 25 mA
I
Controlled edge rates to minimize ground bounce
I
No glitch on power-up
I
Supports hot insertion
I
Low standby current
I
Operating power supply voltage range of 2.3 V to 5.5 V
I
0 Hz to 400 kHz clock frequency
NXP Semiconductors
PCA9553
4-bit I
2
C-bus LED driver with programmable blink rates
I
ESD protection exceeds 2000 V HBM per JESD22-A114, 150 V MM per
JESD22-A115 and 1000 V CDM per JESD22-C101
I
Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
I
Packages offered: SO8, TSSOP8 (MSOP8), HVSON8
3. Ordering information
Table 1.
Ordering information
Package
Name
PCA9553D/01
PCA9553D/02
PCA9553DP/01
PCA9553DP/02
PCA9553TK
[2]
PCA9553TK/02
[1]
[2]
Also known as MSOP8.
PCA9553TK uses version /01 address.
Type number
Description
plastic small outline package; 8 leads;
body width 3.9 mm
Version
SOT96-1
SOT505-1
SO8
TSSOP8
[1]
plastic thin shrink small outline package; 8 leads;
body width 3 mm
HVSON8
plastic thermal enhanced very thin small outline
SOT908-1
package; no leads; 8 terminals; body 3
×
3
×
0.85 mm
4. Marking
Table 2.
Marking codes
Marking code
9553/1
9553/2
P53/1
P53/2
P53/1
P53/2
Type number
PCA9553D/01
PCA9553D/02
PCA9553DP/01
PCA9553DP/02
PCA9553TK
PCA9553TK/02
PCA9553_6
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 06 — 29 December 2008
2 of 26
NXP Semiconductors
PCA9553
4-bit I
2
C-bus LED driver with programmable blink rates
5. Block diagram
PCA9553
INPUT
REGISTER
I
2
C-BUS
CONTROL
SCL
SDA
INPUT
FILTERS
LED SELECT (LSn)
REGISTER
0
1
PRESCALER 0
REGISTER
OSCILLATOR
V
SS
002aad745
V
DD
POWER-ON
RESET
PWM0
REGISTER
PWM1
REGISTER
LEDn
BLINK0
BLINK1
PRESCALER 1
REGISTER
Only one I/O shown for clarity.
Fig 1.
Block diagram
PCA9553_6
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 06 — 29 December 2008
3 of 26
NXP Semiconductors
PCA9553
4-bit I
2
C-bus LED driver with programmable blink rates
6. Pinning information
6.1 Pinning
LED0
LED1
1
8
V
DD
SDA
LED0
LED1
1
2
8
V
DD
2
PCA9553D/01
7
LED2 3
PCA9553D/02
6 SCL
V
SS
4
002aad678
PCA9553DP/01
7 SDA
LED2 3
PCA9553DP/02
6 SCL
V
SS
4
002aad679
5
LED3
5
LED3
Fig 2.
Pin configuration for SO8
Fig 3.
PCA9553TK
PCA9553TK/02
Pin configuration for TSSOP8
terminal 1
index area
LED0
LED1
LED2
VSS
1
2
3
4
8
7
6
5
V
DD
SDA
SCL
LED3
002aad680
Transparent top view
Fig 4.
Pin configuration for HVSON8
6.2 Pin description
Table 3.
Symbol
LED0
LED1
LED2
V
SS
LED3
SCL
SDA
V
DD
[1]
Pin description
Pin
1
2
3
4
[1]
5
6
7
8
Description
LED driver 0
LED driver 1
LED driver 2
supply ground
LED driver 3
serial clock line
serial data line
supply voltage
HVSON8 package die supply ground is connected to both V
SS
pin and exposed center pad. V
SS
pin must
be connected to supply ground for proper device operation. For enhanced thermal, electrical, and board
level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad
on the board and for proper heat conduction through the board, thermal vias need to be incorporated in the
PCB in the thermal pad region.
PCA9553_6
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 06 — 29 December 2008
4 of 26
NXP Semiconductors
PCA9553
4-bit I
2
C-bus LED driver with programmable blink rates
7. Functional description
Refer to
Figure 1 “Block diagram”.
7.1 Device address
Following a START condition the bus master must output the address of the slave it is
accessing. The address of the PCA9553/01 is shown in
Figure 5
and PCA9553/02 in
Figure 6.
PCA9553TK uses the version /01 address.
slave address
1
1
0
0
0
1
0
R/W
1
1
slave address
0
0
0
1
1
R/W
002aad742
002aad743
Fig 5.
PCA9553/01 slave address
Fig 6.
PCA9553/02 slave address
The last bit of the address byte defines the operation to be performed. When set to logic 1
a read is selected, while a logic 0 selects a write operation.
7.2 Control register
Following the successful acknowledgement of the slave address, the bus master will send
a byte to the PCA9553 which will be stored in the Control register.
0
0
0
AI
0
B2
B1
B0
Auto-Increment
flag
register address
002aad744
Reset state: 00h
Fig 7.
Control register
The lowest 3 bits are used as a pointer to determine which register will be accessed.
If the Auto-Increment flag is set, the three low order bits of the Control register are
automatically incremented after a read or write. This allows the user to program the
registers sequentially. The contents of these bits will rollover to ‘000’ after the last register
is accessed.
When the Auto-Increment flag is set (AI = 1) and a read sequence is initiated, the
sequence must start by reading a register different from ‘0’ (B2 B1 B0
≠
0 0 0).
Only the 3 least significant bits are affected by the AI flag.
Unused bits must be programmed with zeroes.
PCA9553_6
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 06 — 29 December 2008
5 of 26
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