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PCA9554N

Description
8-bit I2C and SMBus I/O port with interrupt
CategoryThe embedded processor and controller    Microcontrollers and processors   
File Size162KB,30 Pages
ManufacturerNXP
Websitehttps://www.nxp.com
Environmental Compliance
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PCA9554N Overview

8-bit I2C and SMBus I/O port with interrupt

PCA9554N Parametric

Parameter NameAttribute value
Source Url Status Check Date2013-06-14 00:00:00
Is it Rohs certified?conform to
MakerNXP
Parts packaging codeDIP
package instructionDIP, DIP16,.3
Contacts16
Reach Compliance Codeunknow
ECCN codeEAR99
JESD-30 codeR-PDIP-T16
JESD-609 codee4
length19.025 mm
Number of digits8
Number of I/O lines8
Number of ports1
Number of terminals16
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Package body materialPLASTIC/EPOXY
encapsulated codeDIP
Encapsulate equivalent codeDIP16,.3
Package shapeRECTANGULAR
Package formIN-LINE
Peak Reflow Temperature (Celsius)245
power supply2.5/5 V
Certification statusNot Qualified
Maximum seat height4.2 mm
Maximum supply voltage5.5 V
Minimum supply voltage2.3 V
Nominal supply voltage3 V
surface mountNO
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceNickel/Palladium/Gold (Ni/Pd/Au)
Terminal formTHROUGH-HOLE
Terminal pitch2.54 mm
Terminal locationDUAL
Maximum time at peak reflow temperature40
width7.62 mm
uPs/uCs/peripheral integrated circuit typePARALLEL IO PORT, GENERAL PURPOSE
PCA9554/PCA9554A
8-bit I
2
C-bus and SMBus I/O port with interrupt
Rev. 07 — 13 November 2006
Product data sheet
1. General description
The PCA9554 and PCA9554A are 16-pin CMOS devices that provide 8 bits of General
Purpose parallel Input/Output (GPIO) expansion for I
2
C-bus/SMBus applications and
were developed to enhance the NXP Semiconductors family of I
2
C-bus I/O expanders.
The improvements include higher drive capability, 5 V I/O tolerance, lower supply current,
individual I/O configuration, 400 kHz clock frequency, and smaller packaging. I/O
expanders provide a simple solution when additional I/O is needed for ACPI power
switches, sensors, push buttons, LEDs, fans, etc.
The PCA9554/PCA9554A consist of an 8-bit Configuration register (Input or Output
selection); 8-bit Input Port register, 8-bit Output Port register and an 8-bit Polarity
Inversion register (active HIGH or active LOW operation). The system master can enable
the I/Os as either inputs or outputs by writing to the I/O configuration bits. The data for
each input or output is kept in the corresponding Input Port or Output Port register. The
polarity of the read register can be inverted with the Polarity Inversion register. All
registers can be read by the system master. Although pin-to-pin and I
2
C-bus address
compatible with the PCF8574 series, software changes are required due to the
enhancements and are discussed in
Application Note AN469.
The PCA9554/PCA9554A open-drain interrupt output is activated when any input state
differs from its corresponding Input Port register state and is used to indicate to the
system master that an input state has changed. The power-on reset sets the registers to
their default values and initializes the device state machine.
Three hardware pins (A0, A1, A2) vary the fixed I
2
C-bus address and allow up to eight
devices to share the same I
2
C-bus/SMBus. The PCA9554A is identical to the PCA9554
except that the fixed I
2
C-bus address is different allowing up to sixteen of these devices
(eight of each) on the same I
2
C-bus/SMBus.
2. Features
I
I
I
I
I
I
I
I
I
I
Operating power supply voltage range of 2.3 V to 5.5 V
5 V tolerant I/Os
Polarity Inversion register
Active LOW interrupt output
Low standby current
Noise filter on SCL/SDA inputs
No glitch on power-up
Internal power-on reset
8 I/O pins which default to 8 inputs
0 Hz to 400 kHz clock frequency

PCA9554N Related Products

PCA9554N PCA9554AN PCA9554BS3
Description 8-bit I2C and SMBus I/O port with interrupt 8-bit I2C and SMBus I/O port with interrupt 8 I/O, PIA-GENERAL PURPOSE, PDSO16
Is it Rohs certified? conform to conform to conform to
Maker NXP NXP NXP
Parts packaging code DIP DIP QFN
package instruction DIP, DIP16,.3 DIP, DIP16,.3 HVQCCN, LCC16,.12SQ,20
Contacts 16 16 16
Reach Compliance Code unknow unknown compli
ECCN code EAR99 EAR99 EAR99
JESD-30 code R-PDIP-T16 R-PDIP-T16 S-PQCC-N16
JESD-609 code e4 e4 e4
length 19.025 mm 19.025 mm 3 mm
Number of digits 8 8 8
Number of I/O lines 8 8 8
Number of ports 1 1 1
Number of terminals 16 16 16
Maximum operating temperature 85 °C 85 °C 85 °C
Minimum operating temperature -40 °C -40 °C -40 °C
Package body material PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code DIP DIP HVQCCN
Encapsulate equivalent code DIP16,.3 DIP16,.3 LCC16,.12SQ,20
Package shape RECTANGULAR RECTANGULAR SQUARE
Package form IN-LINE IN-LINE CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
Peak Reflow Temperature (Celsius) 245 245 260
power supply 2.5/5 V 2.5/5 V 2.5/5 V
Certification status Not Qualified Not Qualified Not Qualified
Maximum seat height 4.2 mm 4.2 mm 1 mm
Maximum supply voltage 5.5 V 5.5 V 5.5 V
Minimum supply voltage 2.3 V 2.3 V 2.3 V
Nominal supply voltage 3 V 3 V 3 V
surface mount NO NO YES
technology CMOS CMOS CMOS
Temperature level INDUSTRIAL INDUSTRIAL INDUSTRIAL
Terminal surface Nickel/Palladium/Gold (Ni/Pd/Au) Nickel/Palladium/Gold (Ni/Pd/Au) Nickel/Palladium/Gold (Ni/Pd/Au)
Terminal form THROUGH-HOLE THROUGH-HOLE NO LEAD
Terminal pitch 2.54 mm 2.54 mm 0.5 mm
Terminal location DUAL DUAL QUAD
Maximum time at peak reflow temperature 40 40 30
width 7.62 mm 7.62 mm 3 mm
uPs/uCs/peripheral integrated circuit type PARALLEL IO PORT, GENERAL PURPOSE PARALLEL IO PORT, GENERAL PURPOSE PARALLEL IO PORT, GENERAL PURPOSE
Source Url Status Check Date 2013-06-14 00:00:00 2013-06-14 00:00:00 -

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