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PDTA113ZU

Description
PNP resistor-equipped transistors; R1 = 1 kW, R2 = 10 kW
CategoryDiscrete semiconductor    The transistor   
File Size104KB,18 Pages
ManufacturerNXP
Websitehttps://www.nxp.com
Environmental Compliance
Download Datasheet Parametric Compare View All

PDTA113ZU Overview

PNP resistor-equipped transistors; R1 = 1 kW, R2 = 10 kW

PDTA113ZU Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerNXP
Parts packaging codeSC-70
package instructionPLASTIC, SC-70, 3 PIN
Contacts3
Reach Compliance Codecompli
ECCN codeEAR99
Other featuresBUILT-IN BIAS RESISTOR RATIO IS 10
Maximum collector current (IC)0.1 A
Collector-emitter maximum voltage50 V
ConfigurationSINGLE WITH BUILT-IN RESISTOR
Minimum DC current gain (hFE)35
JESD-30 codeR-PDSO-G3
JESD-609 codee3
Humidity sensitivity level1
Number of components1
Number of terminals3
Maximum operating temperature150 °C
Package body materialPLASTIC/EPOXY
Package shapeRECTANGULAR
Package formSMALL OUTLINE
Peak Reflow Temperature (Celsius)260
Polarity/channel typePNP
Maximum power dissipation(Abs)0.2 W
Certification statusNot Qualified
surface mountYES
Terminal surfaceTin (Sn)
Terminal formGULL WING
Terminal locationDUAL
Maximum time at peak reflow temperature30
transistor applicationsSWITCHING
Transistor component materialsSILICON
PDTA113Z series
PNP resistor-equipped transistors; R1 = 1 kΩ, R2 = 10 kΩ
Rev. 04 — 2 September 2009
Product data sheet
1. Product profile
1.1 General description
PNP resistor-equipped transistors.
Table 1.
Product overview
Package
NXP
PDTA113ZE
PDTA113ZK
PDTA113ZM
PDTA113ZS
[1]
PDTA113ZT
PDTA113ZU
[1]
Type number
NPN complement
JEITA
SC-75
SC-59
SC-101
SC-43A
-
SC-70
PDTC113ZE
PDTC113ZK
PDTC113ZM
PDTC113ZS
PDTC113ZT
PDTC113ZU
SOT416
SOT346
SOT883
SOT54 (TO-92)
SOT23
SOT323
Also available in SOT54A and SOT54 variant packages (see
Section 2).
1.2 Features
I
Built-in bias resistors
I
Simplifies circuit design
I
Reduces component count
I
Reduces pick and place costs
1.3 Applications
I
General purpose switching and
amplification
I
Inverter and interface circuits
I
Circuit drivers
1.4 Quick reference data
Table 2.
Symbol
V
CEO
I
O
R1
R2/R1
Quick reference data
Parameter
collector-emitter voltage
output current (DC)
bias resistor 1 (input)
bias resistor ratio
Conditions
open base
Min
-
-
0.7
8
Typ
-
-
1
10
Max
−50
−100
1.3
12
Unit
V
mA
kΩ

PDTA113ZU Related Products

PDTA113ZU PDTA113Z PDTA113ZE PDTA113ZK PDTA113ZM PDTA113ZS PDTA113ZT
Description PNP resistor-equipped transistors; R1 = 1 kW, R2 = 10 kW PNP resistor-equipped transistors; R1 = 1 kW, R2 = 10 kW PNP resistor-equipped transistors; R1 = 1 kW, R2 = 10 kW PNP resistor-equipped transistors; R1 = 1 kW, R2 = 10 kW PNP resistor-equipped transistors; R1 = 1 kW, R2 = 10 kW PNP resistor-equipped transistors; R1 = 1 kW, R2 = 10 kW PNP resistor-equipped transistors; R1 = 1 kW, R2 = 10 kW
Is it lead-free? Lead free - Lead free - Lead free - Lead free
Is it Rohs certified? conform to - conform to conform to conform to conform to conform to
Maker NXP - NXP - NXP - NXP
Parts packaging code SC-70 - SC-75 SOT-23 SC-101 TO-92 SOT-23
package instruction PLASTIC, SC-70, 3 PIN - PLASTIC, SC-75, 3 PIN SMALL OUTLINE, R-PDSO-G3 1 X 0.60 MM, 0.50 MM HEIGHT, LEADLESS, ULTRA SMALL, PLASTIC, SC-101, 3 PIN CYLINDRICAL, O-PBCY-T3 PLASTIC PACKAGE-3
Contacts 3 - 3 3 3 3 3
Reach Compliance Code compli - compli unknow compli unknow compli
ECCN code EAR99 - EAR99 EAR99 EAR99 EAR99 EAR99
Other features BUILT-IN BIAS RESISTOR RATIO IS 10 - BUILT-IN BIAS RESISTOR RATIO IS 10 BUILT-IN BIAS RESISTOR RATIO IS 10 BUILT-IN BIAS RESISTOR RATIO IS 10 BUILT-IN BIAS RESISTOR RATIO IS 10 BUILT-IN BIAS RESISTOR RATIO IS 10
Maximum collector current (IC) 0.1 A - 0.1 A 0.1 A 0.1 A 0.1 A 0.1 A
Collector-emitter maximum voltage 50 V - 50 V 50 V 50 V 50 V 50 V
Configuration SINGLE WITH BUILT-IN RESISTOR - SINGLE WITH BUILT-IN RESISTOR SINGLE WITH BUILT-IN RESISTOR SINGLE WITH BUILT-IN RESISTOR SINGLE WITH BUILT-IN RESISTOR SINGLE WITH BUILT-IN RESISTOR
Minimum DC current gain (hFE) 35 - 35 35 35 35 35
JESD-30 code R-PDSO-G3 - R-PDSO-G3 R-PDSO-G3 R-PBCC-N3 O-PBCY-T3 R-PDSO-G3
JESD-609 code e3 - e3 e3 e3 e3 e3
Humidity sensitivity level 1 - 1 - 1 - 1
Number of components 1 - 1 1 1 1 1
Number of terminals 3 - 3 3 3 3 3
Maximum operating temperature 150 °C - 150 °C - 150 °C - 150 °C
Package body material PLASTIC/EPOXY - PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
Package shape RECTANGULAR - RECTANGULAR RECTANGULAR RECTANGULAR ROUND RECTANGULAR
Package form SMALL OUTLINE - SMALL OUTLINE SMALL OUTLINE CHIP CARRIER CYLINDRICAL SMALL OUTLINE
Peak Reflow Temperature (Celsius) 260 - 260 NOT SPECIFIED 260 NOT SPECIFIED 260
Polarity/channel type PNP - PNP PNP PNP PNP PNP
Maximum power dissipation(Abs) 0.2 W - 0.15 W 0.25 W 0.25 W 0.5 W 0.25 W
Certification status Not Qualified - Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified
surface mount YES - YES YES YES NO YES
Terminal surface Tin (Sn) - Tin (Sn) TIN Tin (Sn) TIN Tin (Sn)
Terminal form GULL WING - GULL WING GULL WING NO LEAD THROUGH-HOLE GULL WING
Terminal location DUAL - DUAL DUAL BOTTOM BOTTOM DUAL
Maximum time at peak reflow temperature 30 - 30 NOT SPECIFIED 30 NOT SPECIFIED 30
transistor applications SWITCHING - SWITCHING SWITCHING SWITCHING SWITCHING SWITCHING
Transistor component materials SILICON - SILICON SILICON SILICON SILICON SILICON

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