WS128K32-XXX
128Kx32 SRAM MODULE, SMD 5962-93187 & 5962-95595
FEATURES
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Access Times of 15, 17, 20, 25, 35, 45, 55ns
MIL-STD-883 Compliant Devices Available
Packaging
66 pin, PGA Type, 1.075" square, Hermetic Ce
ramic HIP (Package 400)
Commercial, Industrial and Military Temperature
Ranges
5 Volt Power Supply
Low Power CMOS
TTL Compatible Inputs and Outputs
Built in Decoupling Caps and Multiple Ground Pins
for Low Noise Operation
Weight:
WS128K32-XG1UX
1
- 5 grams typical
WS128K32-XG1TX - 5 grams typical
WS128K32-XG2UX - 8 grams typical
WS128K32-XG2LX - 8 grams typical
WS128K32-XH1X - 13 grams typical
WS128K32-XG4TX
1
- 20 grams typical
All devices are upgradeable to 512Kx32
68 lead, 40mm CQFP (G4T)
1
, 3.56mm (0.140")
(Package 502)
68 lead, 22.4mm CQFP (G2U), 3.56mm (0.140"),
(Package 510)
68 lead, 22.4mm (0.880") square, CQFP (G2L),
5.08mm (0.200") high, (Package 528).
68 lead, 23.9mm Low Profile CQFP (G1U)
1
,
3.57mm (0.140"), (Package 519)
68 lead, 23.9mm Low Profile CQFP (G1T), 4.06
mm (0.160"), (Package 524)
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Organized as 128Kx32; User Configurable as
256Kx16 or 512Kx8
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Note 1: Package Not Recommended For New Design
FIG. 1
P
IN
C
ONFIGURATION
F
OR
WS128K32N-XH1X
T
OP
V
IEW
P
IN
D
ESCRIPTION
I/O
0-31
Data Inputs/Outputs
A
0-16
WE
1-4
CS
1-4
OE
V
CC
GND
NC
Address Inputs
Write Enables
Chip Selects
Output Enable
Power Supply
Ground
Not Connected
B
LOCK
D
IAGRAM
May 2003 Rev. 12
1
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
WS128K32-XXX
FIG. 2
P
IN
C
ONFIGURATION
F
OR
WS128K32-XG4TX
1
T
OP
V
IEW
P
IN
D
ESCRIPTION
I/O
0-31
A
0-16
WE
CS
1-4
OE
V
CC
GND
NC
Data Inputs/Outputs
Address Inputs
Write Enables
Chip Selects
Output Enable
Power Supply
Ground
Not Connected
B
LOCK
D
IAGRAM
Note 1: Package Not Recommended For New Design
FIG. 3
P
IN
C
ONFIGURATION
F
OR
WS128K32-XG2UX, WS128K32-XG2LX, WS128K32-XG1TX
AND
WS128K32-XG1UX
1
P
IN
D
ESCRIPTION
T
OP
V
IEW
I/O
0-31
A
0-16
WE
1-4
CS
1-4
OE
V
CC
GND
NC
Data Inputs/Outputs
Address Inputs
Write Enables
Chip Selects
Output Enable
Power Supply
Ground
Not Connected
B
LOCK
D
IAGRAM
Note 1: Package Not Recommended For New Design
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
2
WS128K32-XXX
A
BSOLUTE
M
AXIMUM
R
ATINGS
Parameter
Symbol
Min
Max
Unit
CS
OE
WE
T
RUTH
T
ABLE
Mode
Data I/O
Power
Operating Temperature
Storage Temperature
Signal Voltage Relative to GND
Junction Temperature
Supply Voltage
T
A
T
STG
V
G
T
J
V
CC
-55
-65
-0.5
+125
+150
Vcc+0.5
150
°C
°C
V
°C
V
H
L
L
L
X
L
X
H
X
H
L
H
Standby
Read
Write
Out Disable
High Z
Data Out
Data In
High Z
Standby
Active
Active
Active
-0.5
7.0
R
ECOMMENDED
O
PERATING
C
ONDITIONS
Parameter
Symbol
Min
Max
Unit
C
APACITANCE
(TA = +25°C)
Parameter
Symbol
Conditions
Max
Unit
OE capacitance
WE
1-4
capacitance
HIP (PGA) H1
CQFP G4T
CQFP G2U/G2L
CQFP G1U/G1T
CS
1-4
capacitance
Data I/O capacitance
Address input capacitance
C
OE
C
WE
V
IN
= 0V, f = 1.0 MHz
V
IN
= 0V, f = 1.0 MHz
50
20
50
20
20
pF
pF
Supply Voltage
Input High Voltage
Input Low Voltage
Operating Temp. (Mil.)
V
CC
V
IH
V
IL
T
A
4.5
2.2
-0.3
-55
5.5
V
CC
+ 0.3
+0.8
+125
V
V
V
°C
C
CS
C
I/O
C
AD
V
IN
= 0V, f = 1.0 MHz
V
I/O
= 0V, f = 1.0 MHz
V
IN
= 0V, f = 1.0 MHz
20
20
50
pF
pF
pF
This parameter is guaranteed by design but not tested.
DC C
HARACTERISTICS
(VCC = 5.0V, GND = 0V, TA = -55°C
TO
+125°C)
Parameter
Sym
Conditions
Min
-15
Max
Min
-17
Max
Min
-20
Max
Min
-25
Max
Units
Input Leakage Current
Output Leakage Current
Operating Supply Current
Standby Current
Output Low Voltage
Output High Voltage
Parameter
I
LI
I
LO
I
CC
I
SB
V
OL
V
OH
Sym
V
CC
= 5.5, V
IN
= GND to V
CC
CS = V
IH
, OE = V
IH
, V
OUT
= GND to V
CC
CS = V
IL
, OE = V
IH
, f = 5MHz, Vcc = 5.5
CS = V
IH
, OE = V
IH
, f = 5MHz, Vcc = 5.5
I
OL
= 8mA, V
CC
= 4.5
I
OH
= -4.0mA, V
CC
= 4.5
Conditions
10
10
600
80
0.4
2.4
2.4
-35
10
10
600
80
0.4
2.4
-45
10
10
600
80
0.4
2.4
-55
10
10
600
60
0.4
µA
µA
mA
mA
V
V
Units
Min
Max
Min
Max
Min
Max
Input Leakage Current
Output Leakage Current
Operating Supply Current
Standby Current
Output Low Voltage
I
LI
I
LO
I
CC
I
SB
V
OL
V
CC
= 5.5, V
IN
= GND to V
CC
CS = V
IH
, OE = V
IH
, V
OUT
= GND to V
CC
CS = V
IL
, OE = V
IH
, f = 5MHz, Vcc = 5.5
CS = V
IH
, OE = V
IH
, f = 5MHz, Vcc = 5.5
I
OL
= 2.1mA, V
CC
= 4.5
2.4
10
10
600
60
0.4
2.4
10
10
600
60
0.4
2.4
10
10
600
60
0.4
µA
µA
mA
mA
V
V
I
OH
= -1.0mA, V
CC
= 4.5
Output High Voltage
V
OH
NOTE:
DC test conditions: VIH = VCC -0.3V, VIL = 0.3V
D
ATA RETENTION
C
HARACTERISTICS
(F
OR
WS128K32L-XXX O
NLY
)
(TA = -55°C
TO
+125°C), (TA = -40°C
TO
+85°C)
Characteristic
Sym
Conditions
Min
Typ
Max
Units
Data Retention Voltage
Data Retention Quiescent Current
Chip Disable to Data Retention Time (1)
Operation Recovery Time (1)
V
CC
ICCDR
T
CDR
T
R
V
CC
= 2.0V
CS
³
VCC -0.2V
V
IN
³
V
CC
-0.2V
or V
IN
- 0.2V
2
-
0
T
RC
-
1
-
-
2
-
-
V
mA
ns
ns
NOTE:
Parameter guaranteed, but not tested.
3
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
WS128K32-XXX
(V
CC
= 5.0V, GND = 0V, T
A
= -55°C
Parameter
Read Cycle
Symbol
-15
Min
Max
-17
Min
Max
Min
-20
Max
AC C
HARACTERISTICS
TO
+125°C)
-25
-35
Max
Min
Max
Min
-45
Max
-55
Min
Max
Units
Min
Read Cycle Time
Address Access Time
Output Hold from Address Change
Chip Select Access Time
Output Enable to Output Valid
Chip Select to Output in Low Z
Output Enable to Output in Low Z
Chip Disable to Output in High Z
Output Disable to Output in High Z
t
RC
t
AA
t
OH
t
ACS
t
OE
t
CLZ
1
t
OLZ
t
CHZ
1
15
15
0
15
10
3
0
12
12
17
17
0
17
10
3
0
12
12
20
20
0
20
12
3
0
12
12
25
25
0
25
15
3
0
12
12
35
35
0
35
20
3
0
20
20
45
45
0
45
25
3
0
20
20
55
55
0
55
30
3
0
20
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
t
OHZ
1
1. This parameter is guaranteed by design but not tested.
(V
CC
= 5.0V, GND = 0V, T
A
= -55°C
Parameter
Write Cycle
Symbol
Min
-15
Max
-17
Min
Max
Min
-20
Max
AC C
HARACTERISTICS
TO
+125°C)
-35
Max
Min
Max
Min
-45
Max
Min
-55
Max
Units
-25
Min
Write Cycle Time
Chip Select to End of Write
Address Valid to End of Write
Data Valid to End of Write
Write Pulse Width
Address Setup Time
Address Hold Time
Output Active from End of Write
Write Enable to Output in High Z
Data Hold Time
t
WC
t
CW
t
AW
t
DW
t
WP
t
AS
t
AH
t
OW
1
15
14
14
10
14
0
0
3
10
0
17
14
15
10
14
0
0
3
10
0
20
15
15
12
15
0
0
3
12
0
25
20
20
15
20
0
0
3
15
0
35
25
25
20
25
0
0
4
20
0
45
30
30
25
30
0
0
4
WS128K32-XXX /
55
EDI8C32128C
45
45
25
45
0
0
4
25
25
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
WHZ
t
DH
1
0
1. This parameter is guaranteed by design but not tested.
FIG. 4
AC T
EST
C
IRCUIT
Parameter
AC T
EST
C
ONDITIONS
Typ
Unit
Input Pulse Levels
Input Rise and Fall
Input and Output Reference Level
Output Timing Reference Level
V
IL
= 0, V
IH
= 3.0
5
1.5
1.5
V
ns
V
V
Notes:
VZ is programmable from -2V to +7V.
IOL & IOH programmable from 0 to 16mA.
Tester Impedance Z0 = 75
W.
VZ is typically the midpoint of VOH and VOL.
IOL & IOH are adjusted to simulate a typical resistive load circuit.
ATE tester includes jig capacitance.
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
4
WS128K32-XXX
FIG. 5
T
IMING
W
AVEFORM
-
READ CYCLE
FIG. 6
W
RITE
C
YCLE
- WE C
ONTROLLED
FIG. 7
W
RITE
C
YCLE
- CS C
ONTROLLED
WS32K32-XHX
5
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
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